BDFN10A054U

Solid-state silicon-avalanche technologyLowoperating and clamping voltageUp to four I/OLines of Protection

Ultra low capacitance: 0.5pFtypical(I/O to I/O)Low Leakage

Low operating voltage:5V

Flow-Through design

IEC COMPATIBILITY (EN61000-4)

IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)IEC 61000-4-4 (EFT) 40A (5/50ns)

IEC 61000-4-5(Lightning) 5A(8/20μs)

Mechanical Characteristics

DFN-10L package (2.5×1.0×0.58mm)

Molding compound flammability rating: UL 94V-0Marking: Marking CodePackaging: Tape and Reel

RoHS/WEEE Compliant

Circuit Diagram

Pin1Pin2Pin4Pin53,84-LineProtectionDFN2.5x1-10LApplications



Digital Visual Interface(DVI)MDDI Ports

DisplayPortTM

Interface

PCI Express

High Definition Multi-Media Interface(HDMI)

eSATA Interfaces

Schematic & PIN Configuration

109876

12345PinIdentificaion1,2,4,5InputLines6,7,9,10OutputLines(NoInternalConnection)3,8GroundPage 1 of 5

Absolute Maximum Rating

RatingPeak Pulse Power( tp=8/20μs)Peak Pulse Current ( tp=8/20μs)ESD per IEC 61000-4-2(Air)ESD per IEC 61000-4-2(contact)Operating TemperatureStorage TemperatureBORN SEMICONDUCTOR

SymbolPPPIppBDFN10A054U

Value1505+/-17+/-12-55 to + 125-55 to +150

UnitsWattsAVESDTJTSTGkV°C°CElectrical Parameters (T=25°C)

SymbolParameterMaximum Reverse Peak Pulse CurrentClamping Voltage @ IPPWorking Peak Reverse VoltageMaximum Reverse Leakage Current @ VRWMBreakdown Voltage @ITTest CurrentForward CurrentForward Voltage @ IFIIFIPPVCVRWMIRVBRITIFVCVBRVRWMIRVFITV VF IPP Electrical Characteristics

ParameterReverse Stand-Off VoltageReverse Breakdown VoltageReverse Leakage CurrentClamping VoltageSymbolVRWMVBRIRVcConditionsAny I/O pin to groundI=1mA Any I/O pin to groundt

MinimumTypicalMaximum5.0UnitsVV6.01150.80.35VRWM=5V,T=25°CAny I/O pin to groundIpp=5A, tp=8/20µsAny I/O pin to groundVR = 0V, f = 1MHz I/O pin to GNDµAVpFpFJunction CapacitanceCjVR = 0V, f = 1MHz Between I/O pins

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BORN SEMICONDUCTORTypical Characteristics

Non-RepetitivePeakPulsePowervs.PulseTime10110BDFN10A054UPowerDeratingcurvePeakPulsePower-Ppp(KW)%ofRatedPowerorIPP10090807060504030201001150W8/20µsWaveform0.1 02550751001251500.010.11101001000

PulseDuration-tp(us)AmbientTemperature-TA(℃)PulseWaveform1101009080WaveformParameters:tr=8ustd=20usClampingVoltagevs.PeakPulseCurrent4035ClampingVoltage-Vc(V)PercentofIpp302520151050012LinetoLine

LinetoGnd706050403020100

e-tTd＝IPP/2Waveformparameters:tr=8ustd=20us051015Time(us)2025303456PeakPulseCurrent-Ipp(A)NormalizedCapacitancevs.ReverseVoltage1.51.41.31.21.11.00.90.80.70.60.50.40.30.20.10InsertionLossS21-I/OtoGNDCH1S21LOG6dB/REF0dB1:-0.086dB900MHz0-6dB-12dB-18dBC(VR)/CJ(VR=0)3122:-0.0336dB1.8GHz3:-0.126dB2.5GHzF=1MHz012345-24dB-30dB-36dB-42dB

Reversevoltage-VR(V)

-48dB1MHzSTAR.030MHz10MHz100MHz13GHzGHzSTOP3000.000000MHz

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BORN SEMICONDUCTORDesign Recommendations for HDMI protection

BDFN10A054UAdding external ESD protection to HDMI ports can bechallenging. First, ESD protection devices have aninherent junction capacitance. Furthermore, addingeven a small amount of capacitance will cause theimpedance of the differential pair to drop. Second,large packages and land pattern requirements causediscontinuities that adversely affect signal integrity. TheBDFN10A054U

are specificallydesigned for protection of high-speed interfaces suchas HDMI.

They present <0.4pF capacitance betweenthe pairs while being rated to handle±8kV ESDcontact discharges (±15kV air discharge) as outlinedin IEC 61000-4-2. Each device is in a leadless SLPpackage that is less than 1.1mm wide. They aredesigned such that the traces flow straight through thedevice. The narrow package and flow-through designreduces

discontinuities and minimizes impact on signalintegrity. This becomes even more critical as signalspeeds increase.

Pin Configuration

Figure 1 is an example of how to route the high speed

differential traces through the SHDFN10A054U. Thesolid line

-

represents the PCB trace. The PCB tracesare used to connect the pin pairs for each line (pin 1 topin 10, pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6).For example, line 1 enters at pin 1 and exits at Pin 10and the PCB trace connects pin 1 and 10 together. Thisis true for lines connected at pins 2, 4, and 5 also. Groundis connected at pins 3 and 8. One largeground pad should be used in lieu of two separatepads. The same layout rules apply for theBDFN10A054U.

HDMIConnector1211109876543211GNDGNDGNDGNDFigure1.FlowthoughlayoutUsingSHDFN10A054U

DesignRecommendationsforHDMIProtection

Good circuit board layout is critical not only for signal integrity, but also for effective suppression of ESD induced transients. For optimum ESD protection, the following guidelines are recommended:

Place the device as close to the connector as possible.This practice restricts ESD coupling into adjacent traces and reduces parasitic inductance.





The ESD transient return path to ground should be kept as short as possible.

Whenever possible, use multiple micro vias connected directly from the device ground pad to the ground plane.Avoid running critical signals near board edges.

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BORN SEMICONDUCTOROutline Drawing –DFN-10L

ADB1098BDFN10A054U76PIN1INDICATOR(LASERMARK)E12345DFN2.5x1-10LDIMENSIONSAaaaCSEATINGPLANEDIMAA1A2bb1INCHESMIN.0200.00NOM.023.001(0.005).006.014.094.035.008.016.098.039.020 BSC.012.01580.0030.004.0170.30.010.018.102.0430.150.352.400.90MAX.026.002MIN0.500.00MILLIMETERSNOM0.580.03(0.13)0.200.402.501.000.50 BSC0.3880.080.100.4250.250.452.601.10MAX0.650.05A2R0.1251E/2LxN2A1b1xNbbbCMCAB2XR0.0757PLACESNeD/2DEbxNbbbMCABeLNNOTES:1.CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).aaabbbNOTES:DIMENSIONSDIMP1PYZ(C)G(Y1)INCHES(.034).008.020.039.008.016.027(.061).061MILLIMETERS(0.875)0.200.501.000.200.400.675(1.55)1.551.CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.CONSULT YOUR MANUFACTURING TO ENSURE YOUR COMPANYS MANNUFACTURING GUIDELINES ARE MET.CGPP1XX1XX1YY1ZPage 5 of 5