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专利名称：Circuit for delaying at least one high bit rate
binary data train
发明人：Michel Le Calvez,Michel Peruyero申请号：US07/273469申请日：19881117公开号：US05113368A公开日：19920512
摘要：A circuit for delaying at least one high bit rate data train, the circuit comprising:first (25) and second (26) first-in-first-out (FIFO) type registers having \"m\" inputs and \"n\"words in series; a binary counter (27) delivering a most significant bit signal (MSB); awrite/read control circuit (28) for controlling writing and reading in said register (25, 26)and comprising: a circuit for switching a clock signal (H) alternatively to each of the tworegisters (25, 26) in order to write in one of the two registers while simultaneouslyreading from the other, and vice versa; a circuit (33, 34) for dynamically resetting saidregisters (25, 26) to zero immediately prior to each write stage; and a circuit (35) forgenerating an output enable signal for controlling said registers to enable the previouslyinput data to be output therefrom after a delay of \"n\" clock periods since the beginningof a write stage.
申请人：ALCATEL THOMSON FAISCEAUX HERTZIENS
代理机构：Christie, Parker & Hale
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