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专利名称：Method for planarizing an interconnect
structure
发明人：Hui Chen,Chun Yan,Wai-Fan Yau申请号：US10683143申请日：20031009
公开号：US20050079703A1公开日：20050414
专利附图：
摘要：A method of forming an interconnect structure (e.g., copper interconnectstructure, and the like) on a semiconductor substrate. The interconnect structure isformed by depositing within trenches and openings formed in an inter-metal dielectric
(IMD) layer a barrier layer and a conductive material. Thereafter, the interconnectstructure is planarized using a two-step process whereby excess conductive material onthe IMD material is removed during the first step using a chemical mechanical polishing(CMD) process. In the second step the barrier layer is removed using a plasma etchprocess. The barrier layer is removed using a gas mixture including a halogen-containinggas.
申请人：Hui Chen,Chun Yan,Wai-Fan Yau
地址：Milpitas CA US,San Jose CA US,Los Altos CA US
国籍：US,US,US
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