VHDL Quartus 八进制计数器源代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER_8 IS PORT (
CLK : IN STD_LOGIC; RS : IN STD_LOGIC;
COUNT_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END COUNTER_8;
ARCHITECTURE BEHAVIORAL OF COUNTER_8 IS
SIGNAL NEXT_COUNT : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL D_COUNT BEGIN
: STD_LOGIC_VECTOR(3 DOWNTO 0);
PROCESS ( CLK,RS ) BEGIN
IF RS = '0' THEN
NEXT_COUNT <= \"0000\";
ELSIF CLK'EVENT AND CLK='1' THEN IF NEXT_COUNT = \"0111\" THEN NEXT_COUNT <= \"0000\"; ELSE
NEXT_COUNT <= NEXT_COUNT + 1; END IF; END IF; END PROCESS; PROCESS ( CLK,RS ) BEGIN
IF RS = '0' THEN D_COUNT <= \"0000\";
ELSIF CLK'EVENT AND CLK='1' THEN
IF NEXT_COUNT = \"0111\" THEN
D_COUNT <= D_COUNT + 1; END IF; END IF; END PROCESS;
COUNT_OUT <= D_COUNT; END BEHAVIORAL;
