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专利名称：Clock control circuit and integrated circuit发明人：Shigenari Kawabata申请号：US10909910申请日：20040802
公开号：US20050030077A1公开日：20050210
专利附图：
摘要：A clock management control circuit of the present invention is a clock controlcircuit for supplying a valid clock signal to a target circuit in accordance with a systemclock signal. When a valid input instruction signal indicating timings of data input to thetarget circuit changes from a disabled state to enabled state, the supply of the clock
signal to the target circuit starts in accordance with the system clock signal, and if a validoutput instruction signal indicating timings of data output from the target circuit changesfrom the enabled state to disabled state, the supply of the clock signal is stopped after alapse of a predetermined time period set externally. The clock control circuit forsupplying the valid clock to the target circuit can therefore be used in common for avariety of waveforms of a valid input flag and a valid output flag.
申请人：Shigenari Kawabata
地址：Kanagawa JP
国籍：JP
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