MB1503

The MB1503 is configured of a 1.1GHz dual-modulus prescaler with 128/129 divide ratio,control signal generator, 16-bit shift register, 15-bit latch, programmable reference divider(binary 14-bit programmable reference counter), 1-bit switch counter, phase comparatorwith phase conversion function, charge pump, crystal oscillator, 19-bit shift register, 18-bitlatch, programmable divider (binary 7-bit swallow counter and binary 11-bit programmablecounter), analog switches, and an intermittent operation control circuit that selects theoperating or stand-by mode depending on the power-save control input state (PS).

The MB1503 operates from a single +5 V supply. Fujitsu’s advanced technology achievesan Icc of 8mA, typical. The stand-by mode current consumption is just 100µA.

MB1503Features

•••••––•––••••

:fIN = 1.1GHz (PIN = –10dBm)

:High-speed dual-modulus prescaler with 128/129divide ratio

Low supply current:ICC = 8mA typ. at 5VPower-saving stand-by mode:100µA

Serial input, 18-bit programmable divider consisting of:Binary 7-bit swallow counter:0 to 127Binary 11-bit programmable counter:16 to 2,047

Serial input 15-bit programmable reference divider consisting of:Binary 15-bit programmable reference counter: 8 to 16,3831-bit switch counter sets prescaler divide ratioOn-chip analog switch for fast lock-upOn-chip charge pump

Wide operating temperature range: –40 to +85°CPlastic 16–pin dual inline package (Suffix : –P)Plastic 16–pin small outline package (Suffix : –PF)High operating frequencyPulse-swallow function

PLASTIC PACKAGE(FPT-16P-M06)

ABSOLUTE MAXIMUM RATINGS (See NOTE)

RatingsSupply VoltageOutput VoltageOutput CurrentStorage TemperatureSymbolVCCVPVOUTIOUTTstgValue–0.5 to +7.0VCC ≤ VP ≤ 10.0–0.5 to VCC +0.5±10–55 to +125UnitVVVmA°CThis device contains circuitry to protect the inputsagainst damage due to high static voltages or electricfields. However, it is advised that normal precautions betaken to avoid application of any voltage higher thanmaximum rated voltages to this high impedance circuit.

PLASTIC PACKAGE(DIP-16P-M04)

NOTE:Permanent device damage may occur if the above Absolute Maximum

Ratings are exceeded. Functional operation should be restricted to theconditions as detailed in the operational sections of this data sheet. Exposureto absolute maximum rating conditions for extended periods may affect devicereliability.

Copyright©1994 by FUJITSULIMITED

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MB1503

PIN ASSIGNMENT

(TOP VIEW)

OSCINOSCOUT

VPVCCDOGNDLDfIN

12345678

161514131211109

PSfRfPBiSWFCLEDataClock

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MB1503

BLOCK DIAGRAM

16PSOSCIN116-bit Shift RegisterOscillatorPS116-bit Shift RegisterTo Lock DetectorPhaseComparatorPS115fROSCOUT215-bit Latch15-bit Latch14fPVP3ProgrammableReference DividerBinary 14-bitReference CounterPhaseCharacteristicsChangingCircuitPS1PS1ChargePumpVCC4SWFromPhaseComparator13BiSWDOFrom ChargePump5IntermittentOperationControl Circuit12FCGND6FromPhaseComparatorLock DetectionCircuitSchmittTrigger11LELD719-bit Shift Register19-bit Shift Register1-bitControlLatchSchmittTrigger10Data18-bit Latch7-bit LatchPS1Programmable DividerPrescalerOutputPS1Binary 7-bitBinary 11-bitProgrammableSwallowCounterCounter11-bit LatchSchmittTrigger9ClockSWfIN8PrescalerMCControl Circuit3

MB1503

PIN DESCRIPTION

Pin No.Pin Name1OSCINI/OIDescriptionProgrammable reference divider inputOscillator inputAn external crystal is connected to this pin.Oscillator outputAn external crystal is connected to this pin.Power supply input for charge pump and analog switchPower supplyCharge pump outputThe phase of the charge pump is reversed depending on the FC input.GroundPhase comparator outputThe output level is high when LD is locked. The output level is low when LD is unlocked.Prescaler inputConnection with an external VCO should be done by AC coupling.Clock input for 19-bit and 16-bit shift registersData is shifted into the shift register on the rising edge of the clock.The Schmitt trigger is contained.Serial data input using binary codeThe last bit of the data is a control bit.When the control bit is high, data is transmitted to the 15-bit latch.When it is low, data is transmitted to the 18-bit latch.The Schmitt trigger input is involved.Load enable signal inputWhen LE is high, the data of the shift register are transferred to a latch, depending on thecontrol bit in the serial data. At the same time, an internal analog switch turns on and the outputof the internal charge pump is connected to the BiSW pin.The Schmitt trigger input is involved.Phase select input of phase comparator (with internal pull-up resistor)When FC is low, the characteristics of the charge pump and phase comparator are reversed.The FC input signal is also used to control the fOUT pin (test pin) of fR or fP.Analog switch outputBiSW is usually in the high-impedance state. When the switch is turned on (LE is high), thestate of the internal charge pump is output.Monitor pin of programmable counter outputMonitor pin of reference counter outputPower save signal inputSet PS low while the system is powered (never use pin 16 as it is opened)PS = High:Operation modePS = Low:Stand-by mode234567OSCOUTVPVCCDOGNDLDfINClockO––O–OII10DataI11LEI12FCI13BiSWO141516fPfRPSOOI4

MB1503

FUNCTIONAL DESCRIPTIONS

Pulse swallow function

The divide ratio can be calculated using the following equation:

fVCO = [(M x N) + A] x fOSC ÷ R (A < N)

fVCO:Output frequency of external voltage controlled oscillator (VCO)N:Preset divide ratio of binary 11-bit programmable counter (16 to 2,047)A:Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)fOSC:Output frequency of the reference frequency oscillatorR:Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383)M:Preset divide ratio of modules prescaler (128)

Serial data input

Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bitprogrammable divider separately.

Binary serial data is input to the Data pin.

One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, storeddata is latched depending on the control data as follows:

Control data

HL

(a)

Destination of serial data15-bit latch18-bit latch

Programmable reference divider ratio

The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The serial 16-bit data format isshown below:

Direction of data shiftControl bitLSBS1S2S3S4S5S6Divide ratio setting bit for prescalerMSBS7S8S9S10S11S12S13S14CSWDivide ratio setting bit for programmable reference counter5

MB1503

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14-bit programmable reference counter divide ratio

Divide ratioR•16383S1400•1S1300•1S1200•1S1100•1S1000•1S900•1S800•1S700•1S600•1S500•1S411•1S300•1S200•1S101•1(Divide ratio = 8 to 16,383)

Notes:1.Divide ratios less than 8 are prohibited

2.SW: This bit selects the divide ratio of the prescaler

SW Low: 128 or 129 (SW must be always be low)

3.S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383)4.C: Control bit: Set high5.Input MSB data first(b)

Programmable divider divide ratio

The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and 11-bit programmablecounter. The serial 19-bit data format is shown below:

Direction of data shiftControl bitLSBS1S2S3S4S5S6S7S8S9S10S11S12S13S14S15MSBS16S17S18CDivide ratio setting bit forswallow counterDivide ratio setting bit for programmable counter6

MB1503

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7-bit swallow counter divide ratioDivideratioA01•127S700•1S600•1S500•1S400•1S300•1S200•1S101•1•

11-bit programmable counter divide ratioDivideratioN1617•2047S1800•1S1700•1S1600•1S1500•1S1400•1S1300•1S1211•1S1100•1S1000•1S900•1S801•1(Divide ratio = 0 to 127)

Notes:1.

2.3.4.5.

(Divide ratio = 16 to 2,047)

Divide ratios less than 16 are prohibited for the 11–bit programmable counterS1 to S7: These bits select the divide ratio of the swallow counter (0 to 127)

S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047)C: Control bit: (Set low)Input MSB data first

Serial data input timing

•

t1 (≥ 1µs) : Data setup timet2 (≥ 1µs) : Data hold timet4 (≥ 1µs) : LE setup time to the rising edge of last clock

t3 (≥ 1µs) : Clock pulse widtht5 (≥ 1µs) : LE pulse width

DataS18 =MSB(SW) (∗1)S17(S14)S10(S8)S9(S7)S1 =LSB(S1)C: Control bit(C: Control bit)ClockLEt1t2t3t5t4∗1 :Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.Note:One bit of data is shifted into the shift register on the rising edge of the clock.7

MB1503

Intermittent operation

Intermittent operation limits power consumption by shutting down or starting the internal circuits according to their necessity. If deviceoperation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined phaserelationship between the reference frequency (fR) and the comparison frequency (fP) and frequency lock is lost.

To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forciblycorrecting the phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set high, thecircuit enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is explainedbelow:••

Operating mode (PS =High Level)

All circuits are operating, and PLL operation is normal.

Stand-by mode (PS = Low level)

Circuits that do not affect operation are powered down to limit current consumption.The current in the power save state is typically 100µA.

At this time, the levels of DO and LD are the same as when the PLL is locked.

Since DO is placed in the high-impedance state and the input voltage of the voltage controlled oscillator (VCO) is set to the voltagein the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO (fVCO) is kept atthe locking frequency.

The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly correcting thephase of the reference and comparison frequencies to limit power consumption.The device must be set in the stand-by mode (PS = low) when it is powered up.

Relationship between the FC input and phase characteristics

The FC pin changes the phase characteristics of the phase comparator. The internal charge pump output level (DO) is reversed,depending on the FC pin input level. The relationship between the FC input level and DO is shown below:

FC = High or openfR > fPfR < fPfR = fP∗1: High impedance

When designing a synthesizer, the FC pin setting depends on the VCO characteristics.

HLZ (∗1)FC = LowLHZ (∗1)1∗:When the VCO characteristics are similar to 1 , set FC high or open.∗:When the VCO characteristics are similar to 2 , set FC low.VCOoutputfrequency2VCO input voltage8

MB1503

Phase comparator output waveform (FC = High)

fRfPLDHDOfR > fPfR = fPZLfR < fPfR < fPfR < fPNotes:1.Phase difference detection range: –2π to +2π2.Spike appearance depends on the charge pump characteristics. Also, the spike is output to diminishdead band.3.When fR > fP or fR < fP, a spike might not appear depending on the charge pump characteristics.4.LD is low when the phase difference is tw or more. LD is high when the phase difference is tw or less forthree or more cycles (when fOSCIN = 12.8MHz, tw = 625 to 1,250ns).Analog switch

The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (DO) is output throughthe BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state.

When LE = high (when the divide ratio of the internal divider is changed): Analog switch = onWhen LE = low (normal operating mode): Analog switch = off

The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up timewhen the PLL channel is changed.

DOCHPLPF–1LPF–2VCOAnalogswitch(Control signal LE)BiSW9

MB1503

RECOMMENDED OPERATING CONDITIONS

ParameterSymbolVCCVPInput VoltageOperating TemperatureVITAGND–40Min4.5ValueTyp5.0VCC ≤ VP ≤ 8.0––VCC+85Max5.5UnitVVV°CSupply VoltageHANDLING PRECAUTIONS

•This device should be transported and stored in anti-static containers.

•This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover work-benches with grounded conductive mats.

•Always turn the power supply off before inserting or removing the device from its socket.•Protect leads with a conductive sheet when handling or transporting PC boards with devices.

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MB1503

ELECTRICAL CHARACTERISTICS

ParameterSymbolMinValueTypMaxUnitConditionWith fIN = 1.1GHz, OSCIN =12MHz, VCC = 5.0V. Inputsare VCC and outputs areopen.With fIN = 1.1GHz, OSCIN =12MHz, VCC = 5.0V. ThePS pin is grounded, remain-ing inputs are at VCC, andoutputs are open.AC coupling. The minimumoperating frequency ismeasured with a 100pF ca-pacitor connected.—————————VCC = 5V—VDO = GND to 8VVCC ≤ VP ≤ 8V———Supply CurrentICC–8.012.0mAStand-by CurrentIPS–100–µAOperating FrequencyfINfIN10–1100MHzOSCINInput SensitivityfINOSCINHigh-level Input VoltageLow-level Input VoltageHigh-level Input CurrentExcept fIN andOSCINData, Clock,LEFCInput CurrentHigh-level Output VoltageLow-level Output VoltageHigh-impedanceCut off CurrentOutput CurrentOSCINExcept DO andOSCOUTDOExcept DO andOSCOUTfOSCPf INVOSCVIHVILIIHIILIFCIOSCVOHVOLIOFFIOHIOLRON––100.5VCC x 0.7–––––4.4–––1.01.0–12––––1.0–1.0–60±50–––––25206––VCC x 0.3–––––0.41.1–––MHzdBmVp–pVVµAµAµAµAVVµAmAmAΩLow-level Input CurrentAnalog Switch ON Resistance11

MB1503

TEST CIRCUIT

(FOR MEASURING PRESCALER INPUT SENSITIVITY)

VCC = 5VX’ talVP = 6V0.1µ1000pP · G50Ω87654321VCC = 5V910111213141516Oscilloscope12

MB1503

APPLICATION EXAMPLE

LPFVCOOutputFromcontrollerPS16fR15fP14BiSWFC1312LE11Data109Clock47K47KMB15131OSCINX’ talC1C20.1µ23OSCOUTVP4VCC5V5DO67GNDLD8fIN1000p6VVP, VPX:C1, C2:Maximum 8VDepends on the crystal parameters13

MB1503

PACKAGE DIMENSIONS

16-LEAD PLASTIC FLAT PACKAGE(CASE No.: FPT-16P-M06)+0.25.400+.010(10.15 )–.008–0.20.0(2.25)MAX(MOUNTING HEIGHT).002(0.05)MIN(STAND OFF HEIGHT)INDEX“B”.307±.016(7.80±0.40).209±.012(5.30±0.30)+0.40.268+.016(6.80 )–.008–0.20.020±.008(0.50±0.20).050(1.27)TYP.018±.004(0.45±0.10)Ø.005(0.13)M+0.05.006+.002(0.15 )–.001–0.02“A”Details of “A” part.016(0.40)Details of “B” part.006(0.15).004(0.10).350(8.) REF.008(0.20).007(0.18)MAX.027(0.68)MAX.008(0.20).007(0.18)MAX.027(0.68)MAXDimensions in inches (millimeters)©1991 FUJITSU LIMITED F16015S-2C14

MB1503

16-LEAD PLASTIC DUAL IN-LINE PACKAGE(CASE No.: DIP-16P-M04)+0.20.770+.008(19.55 )–.012–0.3015°MAXINDEX-1.244±.010(6.20±0.25).300(7.62)TYPINDEX-2.039+.012–0+0.30(0.99 )–0.060+.012–0+0.30(1.52 )–0.010±.002(0.25±0.05).172(4.36)MAX.118(3.00)MIN.100(2.54)TYP.050(1.27)MAX.020(0.51)MIN.018±.003(0.46±0.08)Dimensions in inches (millimeters)©1991 FUJITSU LIMITED D16033S-2C15