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专利名称：Debug circuit
发明人：Yasushi Ueda,Makoto Okazaki申请号：US10939406申请日：20040914
公开号：US20050066232A1公开日：20050324
专利附图：
摘要：The present invention provide a debug circuit which has a structure in which aconversion block latches plural internal signals which are supposed to be effective infinding a cause of a malfunction and are outputted from a selection block, using a signalthat is outputted from a timing generation block, converts these signals into serial data,
and outputs the serial data to an output block, thereby observing plural signals in the LSIusing fewer external pins, and performing analysis of the malfunction of the LSI speedyand reliably.
申请人：Yasushi Ueda,Makoto Okazaki
地址：Saijo-shi JP,Niihama-shi JP
国籍：JP,JP
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