HDMI信号测试指南

Physical Layer Compliance Testing for HDMI UsingTDSHT3 HDMI Compliance Test Software

Introduction

Termed as the catalyst for the DTV revolution,

High-Definition Multimedia Interface (HDMI) technologyis on the threshold of mass adoption. Content providers,system operators and consumer electronics (CE)manufacturers are rallying behind this standard. As a result, the focus is now on demonstrating compliance to tests defined by HDMI standards.Design and validation engineers need tools to

improve efficiency by performing a wide range ofstandards-required tests quickly and reliably. This application note describes various tests thatensure validation, the challenges faced while testingcomplex HDMI signals and how oscilloscope-residenttest software enables unprecedented efficiencyimprovements with reliable results and unparalleledautomation to perform a wide range of tests (includingthe Sink tests).

Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application NoteBasics

HDMI leverages on the successful transition minimizeddifferential signaling (S) technology. The differentialsignals are +3.3 Volts, terminated in 50 Ωwith nominalamplitude transitions of 500 mV (+2.8 V to +3.3 V).The voltage swing can vary from 150 mV to 800 mV.The signals have rise times of the order of 100 ps. The data rates on a single link can range from 25Mpps to 165 Mpps (Mpps = Mega pixel per second).Since each pixel is represented by 10 bits of data, thebit times, popularly referred as TBIT, can go down to606 ps. A typical HDMI data signal is depicted in

Figure 1. Most of the margins are defined with respectto TBIT– i.e. bit times for data signal.

The S transmission link comprises of three datachannels and one clock channel. Two S links canbe used to achieve higher data rates up to 330 Mpps.Figure 2 depicts the logical links of the S signaling.Physical Layer HDMI Compliance Standards

To ensure reliable information transmission and inter-operability, industry standards specify requirementsfor the network’s physical layer. The HDMI Specifications [1]and, more specifically, the HDMI Compliance TestSpecifications (or CTS) [2]define an array of compliancetests for HDMI physical layer.

Figure 3 illustrates the major elements of the HDMItransmission system – source, cable and sink. TheSource signals are characterized at TP1 while the sinkdevices are tested at TP2 to ensure that they are

within standard margins. For testing cables, measure-ments need to be performed at both TP1 and TP2.Measuring at TP1 ensures measurements at TP2 areperformed under known environments.

2www.tektronix.com/hdmiFigure 1.

Figure 2.

Figure 3.

Physical Layer Compliance testing for HDMI using TDSHT3 HDMI

Application Note

While it is recommended to perform as many tests as possible, the core tests are extremely critical for compliance. The table below summarizes some of the core tests:

ElectricalSignalsTestCTS Test IDTest PointSource Clock and/or DataData Eye DiagramClock JitterClock Duty CycleOvershoot/UndershootRise/Fall TimeInter-pair SkewInter-pair SkewIntra-pair SkewLow Level Output Voltage (VL)7-107-97-87-57-47-67-67-77-2TP1TP1TP1TP1TP1TP1TP1TP1TP1TP2TP2TP2TP2TP1,TP2Data-DataSingle-endedSink Jitter Tolerance8-7Minimum Differential Sensitivity8-5Intra-pair Skew8-6Differential Impedance8-8Cable Data Eye Diagram5-3Source Electrical Tests

These tests are performed on the clock and/or data

signals at TP1. Considering the test setups, these canbe further grouped as Clock-Data, Data-Data andSingle-ended tests. The following sections will discuss these tests in more details.1.Clock-Data Testsa.Data Eye Diagram Test

The objective of this test is to ensure the differentialdata has adequate “eye-opening” to enable effectiverecovery at the sink device after transmission. Thedata is clocked with respect to the recovered-clockand presented in a window size of +1.0 TBIT.

Comparison to mask determines pass or fail andanalysis of data jitter provides useful information on signal integrity.

Figure 4.

The standard clearly delineates the method for clockrecovery. The clock is recovered using a PLL functionshown in Figure 4.

To ensure adequate representation of signal charac-teristics, the CTS specifies a minimum oscilloscoperecord length to acquire the data signal. This ensuresthat at least 400,000 unit intervals (or TBIT) are

accumulated for building the eye diagram. With 16 Mrecord length, 400,000 unit intervals can be capturedfor lower resolution signals, and over 2.6 M UI forhigher resolution devices.

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Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application Note

Figure 5* shows a screen-shot of eye diagram testbeing performed on the oscilloscope. The mask isshifted left until a violation occurs. This testingmethodology requires accurate slicing techniques.Notice the tight margins, which imply strict disciplinein violation detection. Typically, oscilloscope screensmay have a pixel resolution of 500 x 400 or higher forthe graticule and Pass-fail testing is based on maskhits resolved by the screen image.

While this can be acceptable for lower HDMI resolutions,for higher speeds, results can often be misleading. Insuch cases it is preferable to perform mask violationtesting down to data sample resolution. If this testwere to be performed using image resolution, theresults would have been incorrect.b.Clock Jitter

At the nerve center of any transmission system is theclock signal. The jitter test checks to ensure that theclock signal is not carrying excessive jitter. In order toperform this test, the clock is referenced to a recoveredclock. The standard defines the same clock recoveryfunction as shown earlier in Figure 4.

The clock signal is plotted with respect to the recoveredclock. Histogram box is placed at the center of theedge and signal span determines the jitter present onthe signal. The measured jitter should be less than0.25*TBITfor compliance.

Traditionally, when measuring jitter using histogrambox, the box is placed at the center of the rising edgeand the height is kept at the minimum. This techniquecan be termed, for sake of convenience, as min-boxapproach.

It is important to recognize that at clock rates of theorder of 165 MHz, number of samples on the edgemight not be very high. In order to overcome the challenge of fewer samples, the size of histogram box could be increased vertically. In essence, it is nolonger the min-box approach. This leads to higher jitter values as depicted in Figure 6.

*Proper slicing techniques avoid jitter accumulation at edges.4www.tektronix.com/hdmiFigure 5.

Figure 6.

Greater insight into jitter is possible by interpolatingsamples and performingthe measurement using themin-box technique. Figure 7 shows jitter measurementusing interpolated samples using min-box approach.Comparing these values to those in Figure 6 demonstrates the effectiveness of interpolated min-box approach.

Another valuable jitter assessment technique is theTime Interval Error (TIE) method. In this case, theedge displacement is obtained for each cycle and the difference between minimum and maximum is presented as peak-to-peak jitter. Here again, interpolation lends higher resolution for precise analysis and testing.

Physical Layer Compliance testing for HDMI using TDSHT3 HDMI

c.Clock Duty Cycle

Duty cycle jitter is an excellent method of assessingdeterministic jitter. The CTS defines the margin to be+10% from the nominal 50% duty cycle. Thus, theTDUTYmeasured should fall within 40% and 60%.It is important that the variance in duty cycle is meas-ured over large number of acquired signals. As perCTS, minimum 10,000-triggered waveforms arerequired for test purposes. Trigger re-arm rates of the oscilloscope take center-stage. Nominally, oscillo-scope trigger re-arm rate are of the order of about100 waveforms (wfms) per sec. This can mean unacceptably long acquisition and test times. Fortunately, there are sophisticated techniques likethe FastAcq acquisition mode on digital phosphoroscilloscopes (DPO) that enhance the trigger re-armrates and deliver over 400,000 wfms/s. Figure 8demonstrates the clock duty cycle test using theFastAcq mode. Notice the richness of information that ensures convincing measurements. d.Overshoot and Undershoot

Overshoot and undershoot tests ensure that signalsremain within prescribed limits. These tests ensurethat the transmitter does not overdrive the channel ordrive the ESD structures to become non-linear andstart interfering. It also ensures interoperability bytesting signals for recoverability.

The CTS standard defines the limit for overshoot as15% and undershoot as 25% of the entire steady-statevoltage swing. The test is performed on the clock aswell as the data pairs. The test requires measurementof several parameters that includes accurate meas-urement of voltage swing (VHand VL) and overshootand undershoots for both rising and falling edges. Inall, this one test requires over six parameters beforedeclaring results.

Application Note

Figure 7.

Figure 8.

Besides the large number of parameters to be measured, it is also very important to ensure themeasurements are performed authentically. It isimportant to maximize the size of the signal on thedisplay in order to use as much A/D range as possi-ble without overdriving. Figure 9 is a good example ofaccurate overshoot measurement technique. Tightmargins require such careful measures for depend-able results.

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Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application Notee.Rise and Fall Time

Rise and fall time tests have been a mainstay in mostphysical layer tests. The limits ensure that signalsdeliver required signal speed and also that EMI iscontained. The CTS specifies the rise or fall timesshould be higher than 75 ps and lower than 0.4 * TBITvalue.

As in the case of clock duty cycle test, this test alsorequires large number of acquisitions. Once again,trigger re-arm rate becomes important. The test canbe easily performed using FastAcq mode on a DPO.f.Clock-Data Inter-pair Skew

Inter-pair skew is an extremely important test toensure interoperability. This test confirms that skewbetween clock and any of the data pairs are withinlimits. The standard prescribes a limit on skew not toexceed 20% of the pixel-time (TPIXEL). This test is alsoperformed between data channels as well. The nextsection on Data-Data tests describes this test in more details.

2. Data-Data Tests (Inter-pair Skew)The inter-pair skew test has several important aspectsto be considered. Firstly, skew can be effectivelymeasured only when both the pairs are transmitting a specific pattern. Secondly, the measurement paths(probes and oscilloscope acquisition system) couldbe introducing their own share of skew. Thirdly, theoscilloscope would need to trigger on specific serialpatterns, also referred as serial triggering capability.Finally, the margins are specified with respect to thepixel time. Hence, it is important to also determine theclock rate accurately.

It is important to eliminate skew in the acquisitionpath. This process is termed as the “De-skew”

process. For accurate results, it is better to performde-skew prior to making this test.

6www.tektronix.com/hdmiFigure 9.

3. Single-Ended Tests

These tests are performed on each pair using single-ended probes. a.Intra-pair Skew

Intra-pair skew test gains significance, as the signalsare differential and reveals several signaling artifacts.Skew within a differential pair is tested and the stan-dards specify a limit of 15% of the bit time (TBIT). As in the case of Inter-pair skew, it is important to perform de-skew prior to performing this test. Thisensures the error due to skew of the probing andacquisition system is minimized.b.Low level Output Voltage (VL)

The VLtest is performed to ensure signal voltage levels are within prescribed limits. The test checks forthe DC voltage levels on the HDMI link for each Ssignal. The CTS specifies that the voltage of the low-levels should fall within 2.7 V and 2.9 V.

In order to ensure compliance, large numbers ofwaveforms are analyzed. Standard prescribes a minimum of 10,000 waveforms. FastAcq helps

perform this test faster. To determine the voltage level,histogrammethod is employed. The statistical maximaof the histogram (the histogram peak) is presented asthe VLand compared against standard limits.

Physical Layer Compliance testing for HDMI using TDSHT3 HDMI

Application Note

At 165 MHz clock rate, the rise times can be between75 ps to 250 ps. Tektronix’ TDS7704B, for example,provides rise times of the order of 60 ps and can beeffectively used for signals with rise times greater than180 ps.

The eye-diagram and clock jitter tests require a minimumof 16 Meg record length. The eye diagram test is performed using two channels (Data and Clock) and16 M should be available for both channels.

Several tests require large numbers of acquisitions(over 10,000 waveforms) and it is imperative to havefast trigger re-arm rates to perform the tests faster.FastAcq mode is available on many Tektronix oscillo-scopes to enable faster testing.

The Inter-pair Skew test requires trigger on a speci-fied serial pattern. Serial triggering capability isessential for performing this test.

Preparing for Source Testsa.The Test Suite

The following table summarizes the equipments requiredto perform the wide range of tests discussed earlier. Additionally, Digital Multimeter, Protocol Analyzer, LCRMeter and I2C Analyzer are required to perform someof the other tests prescribed by the CTS standard.b.Test Equipment - Important ConsiderationsWhile choosing the right equipment for your testsetup, it is important to understand various aspects that need to be addressed. Some of these aspects are:

Digital Storage Oscilloscope

System performance drives measurement accuracy. Itis important to consider the rise times of your HDMIsignals while selecting the bandwidth required. A

quick calculation on resolution supported, refresh rateand blanking period would provide a good indicatorof the TBITvalues. The TBITvalues can be used toapproximate the rise time of the HDMI signal (~0.2 to0.3*TBIT).

TestDigital OscilloscopeDifferential ProbesSingle-ended ProbesTPA-P Test Adapter SetDC PowerSupplyEDID EmulatorEye DiagramClock JitterDuty CycleOver/UndershootRise/Fall TimeInter-pair SkewIntra-pair SkewOutput Low VLNotes••••••••16 M RL,ST••••••••> 2 nos.2 nos.••••••••1 set••••••••3.3 V••••••••From SIwww.tektronix.com/hdmi7

Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application NoteDifferential Probes

The HDMI S signaling employs differential trans-mission system. Differential probes, with their high

common-mode rejection, high sensitivity and responseaccuracy and low noise floor are well suited for thispurpose. Considering the high signaling rates andtight margins, it is imperative to understand variousaspects and options for probing. The primer –

High-speed Differential Signaling and Measurements (3)provides in-depth understanding of these aspects.Because differential probes have two identical inputpins, making reliable connections is generally morechallenging. It is important to carefully plan the

connections to the test adapters that provide square-pins. Although there is a long list of probe tip

adapters, each option must be weighed thoughtfullyprior to employing any technique. For example, twoTektronix P7350SMA probes could be connected

using TPA-P-TDR adaptor, which enables connectionsthrough SMA for reliable results.

The Tektronix primer dwells into finer details of eachof these options. Variable spacing adapters, for

instance, could result in excessive overshoot. Thoughinconvenient, soldering to the test points offers thebest results. The P7380 probe from Tektronix offers a variety of probe tips that allow soldering or holdingthe probe using a probe-positioner or a handheldprobe housing to allow for point-to-point probing.Probe bandwidth is another important factor to beconsidered. Again, depending on signal rise times,probes should be chosen to ensure its rise times arefast enough to ensure signal fidelity at the measuringinstrument. Tektronix oscilloscopes and probes offersystem bandwidths right up to the probe tip.Test Adapter

Reliable connections are key to maintaining precisionand signal integrity. There are two types of testadapter sets available. For most of the Sourcedevices, the plug-type adapters (TPA-P) are well suited for making the primary connection to theDevice-under-test (DUT). Figure 10 shows a TPA-Pplug-type test adapter.

8www.tektronix.com/hdmiFigure 10.

Automation Tools

Compliance to Source tests implies performing a widerange of tests reliably. Tight margins and complex testprocedures makes these tests very time-consuming.Most of the tests need to be performed under optimalconditions and users need to be an expert in HDMItechnology as well as usage of test equipment. Byany measure, a daunting task.

TDSHT3 discussed later in this document enablesquick and reliable tests. Authentic measurement tech-niques ensure results that are reliable and automationrelieves users of laborious and tedious test processes.c.Test Setup for Source Tests

See Figure 11 for Clock Data and Data-Data Tests.See Figure 12 for Single-ended Tests.d.Getting the test signals from DUT

– Configure the EDID Emulator: This emulates a Sink device to enable handshaking of signals.Using a PC-based software, set the EDID Emulator to the desired resolution settings.

– Provide external power supply: Enables voltage across pull-up resistors.

– There are no specified test patterns required and hence, any HDMI patterns generated by the Source DUT is adequate. For example, any DVD played on a DVD-player would generate required test signals.Refer to the test setups described above for connection details.

Physical Layer Compliance testing for HDMI using TDSHT3 HDMI

Application Note

Figure 11.

Figure 12.

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Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application Note

Sink Electrical Tests

These tests are performed at the HDMI connector atthe Sink Device at TP2. The following sections will discuss these tests in more details.1.Jitter Tolerance Tests

One of the most critical characteristics of a sink

device is its tolerance to specified levels of jitter in thesignals. The standard defines the limit as 0.3*TBIT. Specified amounts of jitter are injected in steps (fromlow to high jitter) into the transmitted S signaluntil the sink device fails to recover the signal. Theamount of jitter, which the sink device is able to tolerate, is compared against limits for compliance.The jitter tolerance testing is performed in the followingbroad steps:

– Determining worst-case Clock-Data skew: The skew in data is varied until the worst point is determined. This test is performed over several iterations as described in Figure 13. The S signal generator is then set to generate this worst-case skew.– Measuring Jitter Margins: Several measurements arecarried out by injecting specified amount of jitter. Three measurements are performed over two test cases – (a) Data Jitter Frequency at 500 KHz and Clock Jitter Frequency at 10 MHz and (b) Data JitterFrequency at 1 MHz and Clock Jitter Frequency at 7 MHz. The three measurements are:1. Data Jitter amplitude (Djw) 2. Worst Data Jitter Amplitude 3. Worst Clock Jitter Amplitude

Figure 14 helps understand measurement criteria forD_JITTER and C_JITTER margins.

The tests need to be performed at all pixel clock ratessupported by the device under test. With variousparameters to be adjusted, and tight margins, this test tends to be extremely complex and takes a verylong time.

10www.tektronix.com/hdmiFigure 13.

Figure 14.

2.Minimum Differential Sensitivity

This test has been very common for most serial standards. The test confirms that the Sink properlysupports interoperability even with attenuated differential voltage swings.

A S signal generator with the ability to changeamplitude is employed for this test. Any Sink-supported27 MHz video format is generated that repeats theRGB gray ramp signals from 0 to 255 during eachvideo period.

Physical Layer Compliance testing for HDMI using TDSHT3 HDMI

The testing starts from 170 mV VDIFFon all pairs andthe differential swing is reduced in steps of 20 mVuntil the Sink device reports error. If the minimum VDIFFto which the Sink responds without error is < 150 mV, the device has passed the test. The teststops when minimum VDIFFreaches 70 mV.Another important element of this test is that it is performed at two different VICM(common-mode voltage) settings, which are 3.0 V and 3.13 V. 3.Intra-pair Skew

The Sink devices also need to be tolerant to intra-pairskew. This test ensures the Sink device allows for timing skew within each S pair. The CTS standarddefines a limit of 0.4*TBITfor intra-pair skew tolerance.The test starts by setting clock and data pairs with noskew and then increasing the intra-pair skew in eachpair (one pair at a time) in steps of 0.1*TBITuntil theSink device outputs an error. The maximum skew witherror-free Sink operation is defined as the Intra-pairskew and is compared against the limit. If greaterthan 0.4*TBIT, the device is termed compliant.

Application Note

4.Differential Impedance

Differential transmission lines used in achieving fastdata rates are very sensitive to impedance matching.Consequently, impedance characterization is a verycrucial test in compliance testing of HDMI. Thethrough-connection impedance has a limit of 15%variance to its 100 Ωspecification. The impedance attermination needs to be tighter as the margins areonly 10% of its characteristic value of 100 Ω.

This test is performed with the Sink device switchedoff. The measurement distance to DUT input connectoris first measured. This is best determined using a TDRmethod where the impedance curve rises sharply to>200 Ωdenoting the distance to the connector.Next, differential impedance values, ZDIFF, are determined for each pair from the input connectoruntil the point where the impedance curve stabilizesto termination impedance. The other non-tested pairsare terminated to 50 Ω. ZDIFFvalues should fall within85 Ωto 115 Ωfor a device to pass the test.To obtain a deeper understanding of TDR tests andmeasurement of controlled impedance, Tektronixoffers some very descriptive application notes (seeReferences 4 and 5).

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Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application Note

Jitter Min. Diff. Intra-pairToleranceSensitivitySkewDifferential RemarksImpedanceDigital Storage OscilloscopeDifferential ProbesData Timing GeneratorArbitrary Waveform GeneratorTDR Sampling OscilloscopeTPA-R Test Adapter SetTPA-P Test Adapter Set50 Ωterminations (6 nos.)SMA-BNC adaptorCable from DTG DC O/P Pin-to-SMA at Bias Tee (2 nos.)SMA Cables (12 nos.)SMA(m) – SMA(f) Cables (2)Mini-Circuits Bias Tee (2 nos.)JAE Cable Emulator (1 each)DC Power SupplyGPIB USB ControllerGPIB Cable••••••••••16M RL > 2 nos.DTG5274 with 3 DTGM30AWG710/B•TDS8200 with80E04 + 80E03013-A012-50••013-A013-50015-1022-01015-1018-00012-1506-00 +015-0671-00 +015-1018-00•••••••••••••••••174-1428-00*1 belowZFBT-4R2GW *174.25,27 MHz•••••••••+5VNI GPIB-USB-B*1:Preferable to have SMA (m) at RFinand SMA (f) at RF+DC output port.Preparing for Sink Testsa.The Test Suite

The table above summarizes the equipment requiredto perform the Sink tests discussed earlier.

Additionally, Digital Multimeter, Protocol Analyzer andLCR Meter are required to perform some of the othertests prescribed by the CTS standard.

b.Test Equipments - Important ConsiderationsWhile choosing the right equipment for your test

setup, it is important to understand important aspectsthat need to be addressed by this equipment. Someof these aspects are

Digital Storage Oscilloscope

The jitter tolerance tests require a minimum of 16 Megrecord length in the oscilloscope.

Data Timing Generator

S Signal Generator plays a pivotal role in the Sinktests. The key challenge for a S signal generatoris to provide a full complement of highly accurate signalsand the ability to precisely control their parameters. For performing minimum differential sensitivity tests, aresolution of 20 mV is required. The intra-pair skew testrequires precise delay settings down to sub-picosecondresolution. Tektronix offers the DTG5274 (with DTGM30modules) that combines the power of a data generatorwith the capabilities of a pulse generator to enablethe Sink tests with highly accurate test signals.Arbitrary Waveform Generator

The jitter tolerance test assumes larger challenges as, both, clock and data jitter need to be varied.Generating jitter frequencies of the order of 10 MHzrequires a combination of signal generators. Sincemargins are tight, precise control is required on jitteramplitude. Tektronix’ AWG710B is the platform ofchoice for generating such levels of performance.

12www.tektronix.com/hdmiPhysical Layer Compliance testing for HDMI using TDSHT3 HDMI

Application Note

TDR Sampling Oscilloscope

Time Domain Reflectometry (TDR) is a powerful andaccurate tool for measuring impedance and length ininterconnects. While fundamental concepts of TDR arerelatively simple, a number of issues must be consideredto make accurate measurements, the foremost beingthe ability to perform true-differential TDR. This is whatmakes the TDS8200 with the 80E04 module the tool ofchoice for making the Differential Impedance test. If the TDR connection is to be probed to the

circuit board, the 80A02 module can be combinedwith P8018.

If testing cables (such as in manufacturing), then theP8018 is not needed and just the the 80A02 with footpedal actuator can be used. This protects from possible operator error in connecting cables.Test Adapter

Just as in Source tests, reliable connections are keyto maintaining precision and signal integrity for Sinktests. There are two types of test adapter sets available.For most of the Sink tests devices, the plug-typeadapters (TPA-P) set and receptacle-type adapters(TPA-R) set are well suited for making the primaryconnection to the Device-under-test (DUT). Figure 15shows a TPA-R plug-type test adapter.

Figure 15.

Automation Tools

Sink tests, as in case of Source tests, take a lot oftime. In case of Sink tests, there is added complexityof controlling several tools to conclude a measurement,along with the challenge of precisely setting jitterparameters. All this makes automation an implicitrequirement.

TDSHT3, discussed later in this document, de-skillsthe entire test process and makes use of GPIB toremotely control various parameters. The TDS7000BDPO connects to the DTG5274 using GPIB cable andto the AWG using a GPIB-USB-B cable or E-Net toGPIB converter (available from National Instruments).

Figure 16.www.tektronix.com/hdmi13

Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application Note

Figure 17.

Figure 18.

c.Test Setup for Sink Tests

Jitter Tolerance Tests (See Figure 16)

Minimum Differential Sensitivity (See Figure 17)Intra-pair Skew tests (See Figure 18)

14www.tektronix.com/hdmiPhysical Layer Compliance testing for HDMI using TDSHT3 HDMI

Cable Electrical Tests

These tests are performed at the HDMI cable at bothTP1 and TP2. The following sections will discuss thesetests in more details.1.Data Eye Diagram Tests

The objective of this test is to ensure the cable relaysthe signal accurately from the Source to the Sink. The cable is expected to cause a certain amount ofdegradation to the signal. The test ensures the level of degradation is low enough to ensure interoperabilitybetween devices.

The signal is first characterized at TP1 prior to

introducing the cable into the transmission system. An HDMI Signal Generator is used to generate Ssignals. The HDMI Signal Generator parameters areadjusted to transmit signals carrying a specified

amount of clock and data jitter. The eye-diagram andjitter tests ensure compliance to these test conditionsand is performed similar to the Source tests.The cable is then connected and the data eye dia-gram is verified again at TP2. The standard clearlydelineates the amount of degradation permitted atTP2 by testing against several conditions:– Mask tests

– Data Jitter is < 0.67 ns (equivalent to 0.5*TBITat 75 MHz)The data jitter is measured using a histogram box.Similar to Source jitter tests, min-box approach

provides great insight. The data jitter measured usingmin-box approach delivers reliable results. Figure 19(TP1) and 20 (at TP2) illustrates a cable eye diagramtest being performed on the oscilloscope.

Application Note

Figure 19.

Figure 20.

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Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application Note

2.Optional (Parametric) Tests

These tests are a very good indicator of the signalintegrity of the cable. The tests are recommended, but not required. These tests are:a. Intra-pair Skewb. Inter-pair Skewc. Far-end Crosstalk

The Intra- and Inter-pair skew tests are performed

using a sampling oscilloscope. The Tektronix TDS8200used for Sink Differential Impedance test can be usedfor these tests using a TDT plug-in. The Tektronix80E04 used for TDR can also be used for this test as it is a dual-channel sampler in addition to a dual-differential TDR step-generator. While the Far-endCrosstalk test is usually performed with a NetworkAnalyzer, use of TDR for crosstalk measurements isgaining favor as the measurements can be performedfaster, less expensively, and far more intuitively withTDR. TDA Systems has some informative applicationnotes on measuring crosstalk with a TDR.Preparing for Cable Testsd.The Test Suite

The following table below summarizes the equipmentsrequired to perform the Sink tests discussed earlier. A network analyzer can be used to perform the Far-end Crosstalk tests.

e.Test Equipments - Important ConsiderationsWhile choosing the right equipment for your testsetup, it is important to understand important

aspects that need to be addressed. Some of these

aspects are:

Digital Storage Oscilloscope

The tests require a minimum of 16 Meg record lengthto ensure compliance to standards. Data jitter needsto be measured. It is also important to recognize that the jitter is measured with respect to the PLL-recovered-clock as described in the Source tests. As recommended earlier, min-box approach is mostappropriate for reliable data jitter measurement.Data Timing Generator

S Signal Generator plays a pivotal role in theCable tests. Tektronix offers the DTG5274 (with

DTGM30 modules) that combines the power of a datagenerator with the capabilities of a pulse generator toenable the Cable tests with highly accurate test signals.Sampling Oscilloscope

The limits for the skew tests require ultra-precisionmeasurements. The TDS8200 with 80E04 or 80E03 modules deliver the required measurement accuracyand resolution for making these tests.Automation Tools

Cable data eye diagram test brings the complexity ofboth Source as well as Sink tests. Complexity of

eye-rendering, accurate data jitter measurement tech-niques coupled with the tedium of controlling severaltools make this test very complex. TDSHT3, discussedlater in this document, makes this test with relativeease. The TDS7000B DPO connects to the DTG5274using a GPIB cable.

LiTek, from Taiwan offers a high-speed cable test solution (LT-4165) that automates several other tests.

Data Eye DiagramIntra-Pair SkewInter-pair SkewFar EndCrosstalkRemarks Digital Storage OscilloscopeDifferential ProbesData Timing GeneratorSampling OscilloscopeTPA-R Test Adapter SetTPA-P Test Adapter Set50 Ωterminations (14 nos.)SMA Cables (8 nos.)GPIB USB ControllerGPIB Cable•••••••••••16 M RL > 2 nos.DTG5274 with 3 DTGM30TDS8200 with 80E03/80E04013-A012-50013-A013-50015-1022-01174-1428-00••National Instruments GPIB-USB-B••••••••••••16www.tektronix.com/hdmiPhysical Layer Compliance testing for HDMI using TDSHT3 HDMI

Application Note

Figure 21.

Figure 22.

Figure 23.

f.Test Setup for Cable Tests

See Figure 21 for Data Eye Diagram Tests.See Figure 22 for Intra-pair Skew Test.See Figure 23 for Inter-pair Skew Test.Introducing TDSHT3

Engineers designing or validating their HDMI physicallayer need to perform thorough validation in-house.There are a wide number of tests that need to be

made. These tests have tight margins requiring

precise measurement techniques and complex controlof a variety of test instruments. The standards alsorequire many of the tests to be performed over various supported pixel resolutions, multiplying the complexity.

TDSHT3 HDMI Compliance Test Software automates acomprehensive range of tests, including Source, Sinkand Cable tests, enabling unprecedented efficiencywith reliable results.

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Physical Layer Compliance Testing for HDMI Using TDSHT3 HDMI

Application Note

Reliable and dependable results

TDSHT3 embeds the HDMI CTS-compliance test procedures, including the software clock recovery(SoftCRU), ensuring dependable results. Accurateeye-rendering and precise violation testing delivercredible results. Sink tests are performed accuratelywith closed-loop measurements that eliminate non-linearities of the test setup to deliver precise jittercomponents for cohesive measurements. Authenticmeasurement techniques and automation eliminateerrors to provide convincing results. Faster Validation Cycles

The unparalleled automation offered on the TDSHT3enables faster validation. Test times for Sink devicesshrink from hours to minutes with TDSHT3 remotelycontrolling the DTG and AWG to automate the complex test process. Its one-button “Select All”

feature demonstrates efficiency by performing multipleSource tests. TDSHT3 instantaneously generates csv-format summaries or detailed reports at a press of a button.

Complete solution for validation

TDSHT3 offers a wide range of tests enabling thoroughverification to standards. Tests offered include Source,Sink and Cable devices. With TDSHT3, convincingvalidation can be performed using a complete solutionthat includes oscilloscopes, arbitrary waveform generators, data timing generators, test fixtures and TDR.

Performing the tests using TDSHT3User can select the entire range of tests by clickingon “Select All” button and run the tests at a press of abutton. The Sink tests are invoked when the Sink tabis pressed.

18www.tektronix.com/hdmiThe user interface allows flexibility in setting up thetests and eliminates confusion.

Sink tests can be easily configured to various jitterparameters like amplitude and frequency while thesoftware manages appropriate file transfer to DTG and AWG for automated testing.

Pressing the Run Test button starts the test processand after performing all the tests, relevant plots are presented and result summary is provided asshown below.

Physical Layer Compliance testing for HDMI using TDSHT3 HDMI

Application Note

Report generation is instantaneous at the press of abutton. The reports can then be easily converted in to popular formats such as portable document filesand others. Summary

Pressing Result Details button provides more information on limits and measured values.

High-Definition Multimedia Interface (HDMI) technologyis witnessing rapid growth. As a result, the focus isnow on demonstrating compliance to standards.

Engineers designing or validating the HDMI physicallayer on their products need to perform a wide rangeof tests, quickly, reliably and efficiently.

The large number of severe tests, coupled with unprece-dentedcomplexity, impose several challenges to thetest engineer. Tight margins require careful measure-ments and thorough understanding of error contributors.TDSHT3 enables efficiency improvements by

performing a wide range of tests quickly and reliably.References1. HDMI Specifications

2. Compliance Test Specifications (CTS)

Reports can also be documented in comma-separated-variable format by pressing the Summary button. This is very useful when testing multiple ports anddocumenting them as a summary. The csv formatallows easy documentation in popular tools like Excel and many others.

The TDSHT3 Quick Start User Manual provides examples of performing HDMI Sink tests.Benefits

The TDSHT3 HDMI Compliance Test Software cutsvalidation cycles from days to minutes. Authentic

measurement techniques and closed loop measurementsensure reliable and dependable results. Its unparalleledautomation shrinks test times and minimizes human-error. Coupled with a wide range of test equipment, it completes the solution for HDMI testing. www.tektronix.com/hdmi19

3. High Speed Differential Data Signaling and Measurements – Tektronix Primer4. Differential Impedance Measurements with the Tektronix 8000B Series Instruments – Tektronix Application Note5. Measuring Controlled Boards with TDR – Tektronix Application Note6. TDSHT3 Quick Start User Manual – Tektronix Manual

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For other areas contact Tektronix,Inc.at:1 (503) 627-7111Updated August 13,2004For Further Information

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Copyright © 2004, Tektronix, Inc. All rights reserved. Tektronix products are covered by U.S. and foreignpatents, issued and pending. Information in this publication supersedes that in all previously published material. Specification and price change privileges reserved. TEKTRONIX and TEK areregistered trademarks of Tektronix, Inc. All other trade names referenced are the service marks,trademarks or registered trademarks of their respective companies. 10/04 FLG/WOW61W-17974-1