专利内容由知识产权出版社提供
专利名称：STRESS REDUCTION MEANS FOR WARP
CONTROL OF SUBSTRATES THROUGHCLAMPING
发明人：Vijayeshwar D. Khanna,Sri M. Sri-Jayantha申请号：US13437309申请日：20120402
公开号：US20130260534A1公开日：20131003
专利附图：
摘要：A method is provided for bonding a semiconductor chip to a packagingsubstrate while minimizing the variation in the solder ball heights and controlling the
stress in the solder balls and the stress in the packaging substrate. During the solderreflow, the warp of the packaging substrate, including the absolute warp, thermal warp,and substrate to substrate variations of the warp, is constrained at a minimal level byproviding a clamping constraint to the packaging substrate. During cool down of thesolder balls, the stresses and strains of the solder joints are maintained at levels that donot cause tear of the solder joints or breakage of the packaging substrate by removingthe clamping constraint. Thus, the bonding process provides both uniform solder heightwith minimized solder non-wets and stress minimization of the solder balls and thepackaging substrate.
申请人：Vijayeshwar D. Khanna,Sri M. Sri-Jayantha
地址：Millwood NY US,Ossining NY US
国籍：US,US
更多信息请下载全文后查看
