P4C188-15DI资料

ULTRA HIGH SPEED 16K x 4STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)– 10/12/15/20/25 ns (Commercial)– 12/15/20/25/35 (Industrial)– 15/20/25/35/45 ns (Military)

Low Power (Commercial/Military)– 715 mW Active – 12/15

– 550/660 mW Active – 20/25/35/45– 193/220 mW Standby (TTL Input)

– 83/110 mW Standby (CMOS Input) P4C188– 15 mW Standby (CMOS Input) (P4C188L Military)

Single 5V±10% Power SupplyData Retention with 2.0V Supply(P4C188L Military)Three-State Outputs

TTL/CMOS Compatible OutputsFully TTL Compatible Inputs

Standard Pinout (JEDEC Approved)– 22-Pin 300 mil DIP– 24-Pin 300 mil SOJ

– 22-Pin 290 x 490 mil LCC

DESCRIPTION

The P4C188 and P4C188L are 65,536-bit ultra high speedstatic RAMs organized as 16K x 4. The CMOS memoriesrequire no clocks or refreshing and have equal access andcycle times. Inputs and outputs are fully TTL-compatible.The RAMs operate from a single 5V±10% tolerance powersupply. With battery backup, data integrity is maintained forsupply voltages down to 2.0V. Current drain is typically 10µA from a 2.0V supply.

Access times as fast as 10 nanoseconds are available,permitting greatly enhanced system speeds. CMOS isutilized to reduce power consumption to a low 715mWactive, 193mW standby and only 5mW in the P4C188Lversion.

The P4C188 and P4C188L are available in 22-pin 300 milDIP, 24-pin 300 mil SOJ and 22-pin LCC packages provid-ing excellent board level densities.

FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATIONS

DIP (P3, D3, C3)LCC (L3)

For SOJ pin configuration, please see end of datasheet.

Document # SRAM112 REV A

1

Revised October 2005

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P4C188/188L

MAXIMUM RATINGS(1)

SymbolVCC

ParameterPower Supply Pin withRespect to GNDTerminal Voltage withRespect to GND(up to 7.0V)

Operating Temperature

Value–0.5 to +7–0.5 toVCC +0.5–55 to +125

UnitV

SymbolTBIASTSTGPTIOUT

ParameterTemperature UnderBias

Storage TemperaturePower DissipationDC Output Current

Value–55 to +125–65 to +150

1.050

Unit°C°CWmA

VTERMTA

V°C

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Grade(2)Military

AmbientTemperature

GND0V0V0V

VCC

5.0V ± 10%5.0V ± 10%5.0V ± 10%

CAPACITANCES(4)

VCC = 5.0V, TA = 25°C, f = 1.0MHzSymbolCINCOUT

ParameterInput CapacitanceOutput Capacitance

ConditionsTyp.UnitVIN = 0VVOUT = 0V

57

pFpF

–55°C to +125°C–40°C to +85°CIndustrial

0°C to +70°CCommercial

DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage(2)SymbolVIHVILVHCVLCVCDVOLVOHILIILO ISB

Parameter

Input High VoltageInput Low VoltageCMOS Input High VoltageCMOS Input Low Voltage

Input Clamp Diode VoltageVCC = Min., IIN = 18 mAOutput Low Voltage(TTL Load)

Output High Voltage(TTL Load)

Input Leakage CurrentOutput Leakage Current

IOL = +8 mA, VCC = Min.IOH = –4 mA, VCC = Min.VCC = Max. Mil.VIN = GND to VCC Com’l.VCC = Max., CE = VIH, Mil.VOUT = GND to VCC Com’l.

Standby Power SupplyCE ≥ VIH Mil.Current (TTL Input Levels)VCC = Max ., Ind./Com’l.

f = Max., Outputs OpenStandby Power SupplyCurrent

(CMOS Input Levels)

CE ≥ VHC Mil.VCC = Max., Ind./Com’l.f = 0, Outputs OpenVIN ≤ VLC or VIN ≥ VHC

2.4–10–5–10–5____________

+10+5+10+540352015

Test Conditions

P4C188MinMax2.2VCC +0.5–0.5(3)–0.5(3)

0.80.2–1.20.42.4–5

n/a–5n/a____________

+5n/a+5n/a40n/a2.7n/a

P4C188L

Unit

MinMax2.2VCC +0.5V–0.5(3)–0.5(3)

0.80.2–1.20.4

VVVVVVµAµAmA

VCC –0.2VCC +0.5VCC –0.2VCC +0.5

ISB1

mA

n/a = Not Applicable

Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS maycause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specificationis not implied. Exposure to MAXIMUM rating conditions for extendedperiods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feet perminute of air flow.

3.Transient inputs with VIL and IIL not more negative than –3.0V and–100mA, respectively, are permissible for pulse widths up to 20 ns.4.This parameter is sampled and not 100% tested.

Document # SRAM112 REV APage 2 of 12

P4C188/188LPOWER DISSIPATION CHARACTERISTICS VS. SPEED

Symbol

Parameter

Temperature

RangeCommercial

ICC

Dynamic Operating Current*

IndustrialMilitary

–10180N/AN/A

–12170180N/A

–15160170170

–20155160160

–25150155155

–35N/A150150

–45N/AN/A145

UnitmAmAmA

*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL

DATA RETENTION CHARACTERISTICS (P4C188L Military Temperature Only)

SymbolVDRICCDRtCDRtR†

Parameter

VCC for Data RetentionData Retention CurrentChip Deselect toData Retention TimeOperation Recovery Time

CE ≥ VCC –0.2V,VIN ≥ VCC –0.2V orVIN ≤ 0.2VTest Conditions

Min2.0

10

0tRC§

15

600

900

Typ.*VCC =

2.0V 3.0V

MaxVCC = 2.0V 3.0V

UnitVµAnsns

*TA = +125°C

§†

tRC = Read Cycle Time

This parameter is guaranteed but not tested.

DATA RETENTION WAVEFORM

Document # SRAM112 REV APage 3 of 12

P4C188/188L

AC CHARACTERISTICS—READ CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

Sym.tRCtAAtACtOHtLZtHZtPUtPD

Parameter

-10

12101022

50

10

022

-12

151212

226

012

-15

201515

236

015

-20

252020

238

0

20

-25

352525

2310

025

-35

453535

23

20

0

35

-45

MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax

4545

Unitnsnsnsnsns

Read Cycle Time10Address AccessTimeChip EnableAccess TimeOutput Hold fromAddress ChangeChip Enable toOutput in Low ZChip Disable toOutput in High ZChip Enable toPower Up TimeChip Disable toPower DownTime

25nsns

45ns

TIMING WAVEFORM OF READ CYCLE NO. 1(5)

TIMING WAVEFORM OF READ CYCLE NO. 2(6)

Notes:

5.CE is LOW and WE is HIGH for READ cycle.

6.WE is HIGH, and address must be valid prior to or coincident with CEtransition LOW.

7.Transition is measured ±200mV from steady state voltage prior tochange with specified loading in Figure 1. This parameter is sampledand not 100% tested.

8.Read Cycle Time is measured from the last valid address to the firsttransitioning address.

Document # SRAM112 REV APage 4 of 12

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P4C188/188LAC CHARACTERISTICS - WRITE CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)Sym.tWCtCW

ParameterWrite Cycle TimeChip EnableTime to

End of WriteAddress Validto End of WriteAddressSet-up TimeWrite PulseWidthAddress HoldTime fromEnd of WriteData Valid toEnd of WriteData HoldTimeWrite Enableto Output inHigh ZOutput Activefrom Endof Write

2-10107

128-12

1310-15

2013-20

2515-25

3525-35

4535-45

MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax

Unitnsns

tAWtAStWPtAH

7080

8090

100100

150130

200150

250250

350350

nsnsnsns

tDWtDHtWZ

50

5

60

6

70

6

80

8

100

10

150

15

205

20

nsnsns

tDW

222233ns

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (9)

Notes:

9.CE and WE must be LOW for WRITE cycle.

10.If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

11.Write Cycle Time is measured from the last valid address to the first

transition address.

12.Transition is measured ±200mV from steady state voltage prior to

change with specified loading in Figure 1. This parameter issampled and not 100% tested.

Document # SRAM112 REV APage 5 of 12

P4C188/188L

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9)

AC TEST CONDITIONS

Input Pulse LevelsInput Rise and Fall TimesInput Timing Reference LevelOutput Timing Reference LevelOutput Load

GND to 3.0V

3ns1.5V1.5V

See Figures 1 and 2

TRUTH TABLE

ModeStandbyReadWrite

CEHLL

WEXHL

OutputHigh ZDOUTDIN

PowerStandbyActiveActive

Figure 1. Output Load

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P4C188/L, care must be takenwhen testing this device; an inadequate setup can cause a normalfunctioning part to be rejected as faulty. Long high-inductance leads thatcause supply bounce must be avoided by bringing the VCC and groundplanes directly up to the contactor fingers. A 0.01 µF high frequency

Figure 2. Thevenin Equivalent

capacitor is also required between VCC and ground. To avoid signalreflections, proper termination must be used; for example, a 50Ω testenvironment should be terminated into a 50Ω load with 1.73V (TheveninVoltage) at the comparator input, and a 116Ω resistor must be used inseries with DOUT to match 166Ω (Thevenin Resistance).

Document # SRAM112 REV APage 6 of 12

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P4C188/188LORDERING INFORMATION

1513 10

SELECTION GUIDE

The P4C188/L is available in the following temperature, speed and package options. The P4C188L is only availableover the Military Temperature range.

Temperature RangeCommercialIndustrialMilitary TemperatureMilitary Processed*PackagePlastic DIPPlastic SOJPlastic DIPPlastic SOJSide Brazed DIPCERDIPLCCSide Brazed DIPCERDIPLCCSpeed (ns)10-10PC-10JCN/AN/AN/AN/AN/AN/AN/AN/A12-12PC-12JC-12PI-12JIN/AN/AN/AN/AN/AN/A15-15PC-15JC-15PI-15JI-15CM-15DM-15LM-15CMB-15DMB-15LMB20-20PC-20JC-20PI-20JI-20CM-20DM-20LM-20CMB-20DMB-20LMB25-25PC-25JC-25PI-25JI-25CM-25DM-25LM-25CMB-25DMB-25LMB35-35PC-35JC-35PI-35JI-35CM-35DM-35LM-35CMB-35DMB-35LMB4545PC-45JC-45PI-45JI-45CM-45DM-45LM-45CMB-45DMB-45LMB* Military temperature range with MIL-STD-883, Class B processing.N/A = Not Available

Document # SRAM112 REV APage 7 of 12

P4C188/188L

SOJ PIN CONFIGURATION

SOJ (J4)

Document # SRAM112 REV APage 8 of 12

Pkg #C3# Pins22 (300 mil)SymbolMinMaxA0.1000.200b0.0140.023b20.0300.060C0.0080.015D1.0501.260E0.2600.310eA0.300 BSCe0.100 BSCL0.1250.200Q0.0150.070S10.005-S20.005-Pkg #D3# Pins22 (300 mil)SymbolMinMaxA-0.225b0.0150.020b20.0450.065C0.0090.012D1.0601.110E0.2900.320eA0.300 BSCe0.100 BSCL0.1250.200Q0.0150.060S10.005-α0°15°Document # SRAM112 REV AP4C188/188LSIDE BRAZED DUAL IN-LINE PACKAGE

Page 9 of 12

P4C188/188L

Pkg #J4# Pins24 (300 mil)SymbolMinMaxA0.1280.148A10.082-b0.0160.020C0.0070.010D0.6200.630e0.050 BSCE0.335 BSCE10.2920.300E20.267 BSCQ0.025-Pkg #L3# Pins22SymbolMinMaxA0.0600.080A10.0500.068B10.0220.028D0.2840.296D10.150 BSCD20.075 BSCD3-0.296E0.4840.496E10.300 BSCE20.150 BSCE3-0.496e0.050 BSChR = .012jR = .012L0.0390.051L10.0390.051L20.0580.072ND4NE7Document # SRAM112 REV ASOJ SMALL OUTLINE IC PACKAGE

Page 10 of 12

Pkg #P3# Pins22 (300 Mil)SymbolMinMaxA-0.210A10.015-b0.0140.022b20.0450.070C0.0080.014D1.1451.165E10.2400.280E0.3000.325e0.100 BSCeB-0.430L0.1150.150α0°15°Document # SRAM112 REV APLASTIC DUAL IN-LINE PACKAGE

P4C188/188LPage 11 of 12

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P4C188/188L

REVISIONS

DOCUMENT NUMBER:DOCUMENT TITLE:REV.ORA

ISSUEDATE1997Oct-05

SRAM112

P4C188 / P4C188L ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS

ORIG. OFCHANGEDABJDB

DESCRIPTION OF CHANGENew Data SheetChange logo to Pyramid

Document # SRAM112 REV APage 12 of 12