P4C174-8PM资料

P4C174

HIGH SPEED 8K x 8

CACHE TAG STATIC RAM

FEATURES

High Speed Address-To-Match - 8 ns MaximumAccess Time

High-Speed Read-Access Time– 8/10/12/15/20/25 ns (Commercial)– 15/20/25 ns (Military)Open Drain MATCH OutputReset Function

8-Bit Tag Comparison Logic

Automatic Powerdown During Long Cycles

Data Retention at 2V for Battery BackupOperation

Advanced CMOS TechnologyLow Power Operation

Package Styles Available — 28 Pin 300 mil DIP

— 28 Pin 300 mil Plastic SOJSingle Power Supply — 5V±10%

DESCRIPTION

The P4C174 is a 65,536 bit high speed cache tag staticRAM organized as 8K x 8. The CMOS memory has equalaccess and cycle times. Inputs are fully TTL-compatible.The cache tag RAMs operate from a single 5V±10%power supply. An 8-bit data comparator with a MATCHoutput is included for use as an address tag comparatorin high speed cache applications. The reset functionprovides the capability to reset all memory locations to aLOW level.

The MATCH output of the P4C174 reflects the compari-son result between the 8-bit data on the I/O pins and

the addressed memory location. 8K Cache lines can bemapped into 1M-Byte address spaces by comparing 20address bits organized as 13-line address bits and 7-page address bits.

Low power operation of the P4C174 is enhanced byautomatic powerdown when the memory is deselected orduring long cycle times. Also, data retention is main-tained down to VCC = 2.0. Typical battery backup appli-cations consume only 30 µW at VCC = 3.0V.

FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION

DIP (C5, P5), SOJ (J5)Document # SRAM118 REV C

1

Revised August 2006

元器件交易网www.cecb2b.com

P4C174

MAXIMUM RATINGS(1)

SymbolVCC

ParameterPower Supply Pin withRespect to GNDTerminal Voltage withRespect to GND(up to 7.0V)

Operating Temperature

Value–0.5 to +7–0.5 toVCC +0.5–55 to +125

UnitV

SymbolTBIASTSTGPTIOUT

ParameterTemperature UnderBias

Storage TemperaturePower DissipationDC Output Current

Value–55 to +125–65 to +150

1.050

Unit°C°CWmA

VTERMTA

V°C

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Grade(2)CommercialCommercial

AmbientTemperature0°C to +70°C0°C to +70°C

GND0V0V

VCC

5.0V ± 10%5.0V ± 10%

CAPACITANCES(4)

VCC = 5.0V, TA = 25°C, f = 1.0MHzSymbolCINCOUT

ParameterInput CapacitanceOutput Capacitance

ConditionsTyp.UnitVIN = 0VVOUT = 0V

57

pFpF

DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage(2)SymbolVIHVILVHCVLCVCDVOLVOHILIILO ISB

Parameter

Input High VoltageInput Low VoltageCMOS Input High VoltageCMOS Input Low Voltage

Input Clamp Diode VoltageVCC = Min., IIN = 18 mAOutput Low Voltage(TTL Load)

Output High Voltage(TTL Load)

Input Leakage CurrentOutput Leakage Current

IOL = +8 mA, VCC = Min.IOH = –4 mA, VCC = Min.VCC = Max. Com’l.VIN = GND to VCC Mil.VCC = Max., CE = VIH, Com’l.VOUT = GND to VCC Mil.

CE ≥ VIH Com’l.Standby Power Supply

Current (TTL Input Levels)VCC = Max ., Mil.

f = Max., Outputs OpenStandby Power SupplyCurrent

(CMOS Input Levels)

CE ≥ VHC Com’l.VCC = Max.,

f = 0, Outputs Open Mil.VIN ≤ VLC or VIN ≥ VHC

2.4–5-10–5-10____________

+5+10+5+102540525

mA

Test Conditions

P4C174MinMax2.2–0.5(3)–0.5(3)

VCC +0.50.80.2–1.20.4

UnitVVVVVVVµAµA

VCC –0.2VCC +0.5

ISB1

mA

n/a = Not Applicable

Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS maycause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specificationis not implied. Exposure to MAXIMUM rating conditions for extendedperiods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feet perminute of air flow.

3.Transient inputs with VIL and IIL not more negative than –3.0V and–100mA, respectively, are permissible for pulse widths up to 20 ns.4.This parameter is sampled and not 100% tested.

Document # SRAM118 REV CPage 2 of 12

元器件交易网www.cecb2b.com

P4C174

DATA RETENTION CHARACTERISTICS (P4C174 Military Temperature Only)

SymbolVDRICCDRtCDRtR†

*TA = +25¹C

§tRC = Read Cycle Time

†

Parameter

VCC for Data RetentionData Retention CurrentChip Deselect toData Retention TimeOperation Recovery Time

Test ConditonsMin2.0

Typ.*VCC = 2.0V 3.0VMaxVCC = 2.0V 3.0V

UnitV

CE ≥ VCC –0.2V,VIN ≥ VCC –0.2Vor VIN ≤ 0.2V

0tRC§

1015600900µAnsns

This parameter is guaranteed but not tested.

DATA RETENTION WAVEFORM

POWER DISSIPATION CHARACTERISTICS VS. SPEED

SymbolICC

Parameter

Dynamic Operating Current*

TemperatureRange

CommercialMilitary

–8200

–10180

–12170

170–15

–20155160

–25150155

UnitmAmA

*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.

Document # SRAM118 REV CPage 3 of 12

元器件交易网www.cecb2b.com

P4C174

AC CHARACTERISTICS—READ CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

SymboltRCtAAtOHtACtLZtHZtOEtOLZtOHZtPU

ParameterRead Cycle TimeAddress AccessTime

Address Change toOutput ChangeChip Enable LOW toOutput ValidChip Enable LOWto Output LOW-Z (1)Chip Enable HIGHto Output HIGH -Z (1)Output Enable LOWto Output ValidOutput Enable LOWto Output LOW-Z (1)Output Enable HIGHto Output HIGH -Z (1)Chip Enable LOW orAddress Change toPowerupPowerup toPowerdown

–8MinMax8

83

83

550

50

003310

–10

1210

3

10

356

05

0

–12Max12

3

12

356

05

015

–15MinMax

15

3

15

388

05

020

–20Min

2520

3

20

3810

08

0

–25

MinMaxMinMaxMinMax

25

Unitnsnsns

25nsns

1012

nsnsns

10nsns

tpUPD

202020202025ns

Note:

1. Transition is measured ± 200 mV from steady state voltage with Output Load B.

READ CYCLE NO. 1 (OE CONTROLLED)(2, 3)

Document # SRAM118 REV CPage 4 of 12

元器件交易网www.cecb2b.com

P4C174

READ CYCLE NO. 2 (ADDRESS CONTROLLED)(2)

READ CYCLE NO. 3 (CE CONTROLLED)(2, 3)

Notes:

1. Transition is measured ±200 mV from steady state voltage withOutput Load B. This parameter is sampled, not 100% tested.2. CE is LOW, OE is LOW, WE is HIGH for READ cycle. CE or WE must be HIGH during address transitions.

3. All address lines are valid no later than the transition of CE to LOW.4. READ cycle time is measured from the last valid address to the first transitioning address.

5. Powerup occurs as a result of any of the following conditions: a) Falling edge of CE.

b) Falling edge of WE (CE active).

c) Any address line transition (CE active).

d) Any Data line transition (CE and WE active).

This device automatically powers down after TPUPD has elapsed from any of the prior conditions. Power dissipation is therefore a function of cycle rate, not CE pulse width.

6. CE is LOW, WE is LOW for WRITE cycle. CE or WE must be HIGH during address transitions.

7. WRITE cycle time is measured from the last valid address to the first transitioning address.

8. OE is LOW for this WRITE cycle to show TWZ and TOW.

Document # SRAM118 REV CPage 5 of 12

元器件交易网www.cecb2b.com

P4C174

AC CHARACTERISTICS - WRITE CYCLE

(VCC = 5V ± 10%, 0°C to +70°C)SymboltWCtCWtAStAWtAHtWPtDWtDHtOWtWZ

Parameter

Write Cycle Time

Chip Enable LOW to End ofWrite

Address Valid to Beginningof Write

Address Valid to End ofWrite

End of Write to AddressChange

Write Pulse WidthData Valid to End of WriteEnd of Write to Data ChangeWrite Enable HIGH to OutputLOW-Z (1)

Write Enable LOW to OutputHIGH-Z (1)

–8870707600

4

–101090909600

4

–121210010010600

4

–151512012012700

5

–2020150150151000

7

–2520150150151000

7

MinMaxMinMaxMinMaxMinMaxMinMaxMinMax

Unitnsnsnsnsnsnsnsnsnsns

WRITE CYCLE NO. 1 (WE CONTROLLED)(6)

WRITE CYCLE NO. 2 (CE CONTROLLED)(6)

Document # SRAM118 REV CPage 6 of 12

元器件交易网www.cecb2b.com

P4C174

AC CHARACTERISTICS - MATCH CYCLE

(VCC = 5.0V ± 10%, 0°C to +70°C)SymboltMCtADMtADMHtCEMtCEMHItOEMHItWEMHItDAMtDAMHParameterMatch Cycle TimeAddress Valid to MATCHValidAddress Change to MATCHChangeChip Enable LOW toMATCH ValidChip Enable HIGH toMATCH HIGHOutput Enable LOW toMATCH HIGHWrite Enable LOW toMATCH HIGHData Valid to MATCH ValidData Change to MATCHChange0–888377777039010103881010100–101212310101212130–121515310101515150–15202031515202015–202525–25MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxUnitnsnsnsnsnsnsnsnsnsMATCH TIMING

Document # SRAM118 REV CPage 7 of 12

元器件交易网www.cecb2b.com

P4C174

AC CHARACTERISTICS - RESET CYCLE

(VCC = 5.0V ± 10%, 0°C to +70°C)SymboltRRCtRPtRPUtRPDtRMHItRIXtRIRtPUR

Parameter

Reset Cycle TimeReset Pulse WidthReset LOW to PowerupReset LOW to PowerdownReset LOW to MATCH HIGHReset LOW to InputsIgnored

Reset LOW to inputsRecognized

Powerup to RESET LOW

00

358

10

–83580

358

00

40

12

–1040100

4010

00

45

15

–1245120

4510

00

50

20

–1550120

5012

00

50

25

–2050150

5015

00

60–2560150

6020

MinMaxMinMaxMinMaxMinMaxMinMaxMinMax

Unitnsnsnsnsnsnsnsns

RESET TIMING

AC TEST CONDITIONS

Input Pulse LevelsInput Rise and Fall TimesInput Timing Reference LevelOutput Load

GND to 3.0V< 3ns1.5V

Outputs Loads A, B & C

TRUTH TABLE

ModeStandbyReadWrite

CEHLL

WEXHL

OutputHigh ZDOUTHigh Z

PowerStandbyActiveActive

Output Timing Reference Level1.5V

Document # SRAM118 REV CPage 8 of 12

元器件交易网www.cecb2b.com

P4C174

OUTPUT LOAD AOUTPUT LOAD BOUTPUT LOAD C

ORDERING INFORMATION

SELECTION GUIDE

The P4C174 is available in the following temperature, speed and package options.

Temperature RangeCommercialMiliitary TemperatureMilitary Processed*Package8Plastic DIPPlastic SOJSide Brazed DIPSide Brazed DIP-8PC-8JCN/AN/ASpeed10-10PC-10JCN/AN/A12-15PC-15JCN/AN/A15-15PC-15JC-15CM-15CMB20-20PC-20JC-20CM-20CMB25-25PC-25JC-25CM-25CMB* Military temperature range with MIL-STD-883, Class B processing.N/A = Not Available

Document # SRAM118 REV CPage 9 of 12

元器件交易网www.cecb2b.com

P4C174Pkg ## PinsSymbolAbb2CDEeAeLQS1S2C528 (300 mil)MinMax-0.2250.0140.0260.0450.0650.0080.018-1.4850.2400.3100.300 BSC0.100 BSC0.1250.2000.0150.0700.005-0.005-SIDE BRAZED DUAL IN-LINE PACKAGEPkg ## PinsSymbolAA1bCDeEE1E2QJ528 (300 mil)MinMax0.1200.1480.078-0.0140.0200.0070.0110.7000.7300.050 BSC0.335 BSC0.2920.3000.267 BSC0.025-SOJ SMALL OUTLINE IC PACKAGE

Document # SRAM118 REV CPage 10 of 12

元器件交易网www.cecb2b.com

Pkg #P5# Pins28 (300 mil)SymbolMinMaxA-0.210A1-b0.0140.023b20.0450.070C0.0080.014D1.3451.400E10.2700.300E0.3000.380e0.100 BSCeB-0.430L0.1150.150α0°15°Document # SRAM118 REV CPLASTIC DUAL IN-LINE PACKAGE

P4C174

Page 11 of 12

元器件交易网www.cecb2b.com

P4C174

REVISIONS

DOCUMENT NUMBER:DOCUMENT TITLE:REV.ORABC

ISSUEDATE1997Oct-05Nov-05Aug-06

SRAM118

P4C174 HIGH SPEED 8Kx8 CACHE TAG STATIC RAM

ORIG. OFCHANGEDABJDBJDBJDB

DESCRIPTION OF CHANGENew Data SheetChange logo to Pyramid

Corrected error in Selection GuideUpdated SOJ package information

Document # SRAM118 REV CPage 12 of 12