PIC16F88

1.0

DEVICE OVERVIEW

This document includes programming specificationsfor the following devices:•PIC16F87•PIC16F88

PIC16F87/88

Both algorithms can be used with the two availableprogramming entry methods. The first method, calledLow-Voltage ICSPTM (LVP for short), applies VDD toMCLR and uses the I/O pin RB3 to enter Programmingmode. When RB3 is driven to VDD from ground, thePIC16F87/88 device enters Programming mode. Thesecond method follows the normal MicrochipProgramming mode entry of holding pins RB6 and RB7low, while raising the MCLR pin from VIL to VIHH(13V±0.5V).

Flash Memory Programming Specification

2.0

PROGRAMMING THE PIC16F87/88

The PIC16F87/88 is programmed using a serialmethod. The Serial mode will allow the PIC16F87/88 tobe programmed while in the user’s system, whichallows for increased design flexibility. Thisprogramming specification applies to PIC16F87/88devices in all packages.

2.2Programming Mode

The Programming mode for the PIC16F87/88 allowsprogramming of user program memory, data memory,special locations used for ID, and the configurationwords.

2.1

Programming Algorithm Requirements

The programming algorithm used depends on theoperating voltage (VDD) of the PIC16F87/88 device.

Algorithm #

12

VDD Range2.0V≤VDD<5.5V4.5V≤VDD≤5.5V

FIGURE 2-1:PIC16F87 18-PIN DIP, SOIC RA2/AN2/CVREFRA3/AN3/C1OUTRA4/T0CKI/C2OUTRA5/MCLR/VPPVSSRB0/INT/CCP1(1)RB1/SDI/SDARB2/SDO/RX/DTRB3/PGM/CCP1(1)123181716RA1/AN1RA0/AN0RA7/OSC1/CLKIRA6/OSC2/CLKOVDDRB7/PGD/T1OSIRB6/PGC/T1OSO/T1CKIRB5/SS/TX/CKRB4/SCK/SCLPIC16F874567151413121110Note1:Location of CCP1 function is determined by CCPMX. 2002 Microchip Technology Inc.DS39607B-page 1

PIC16F87/88

FIGURE 2-2:PIC16F87 20-PIN SSOP RA2/AN2/CVREFRA3/AN3/C1OUTRA4/T0CKI/C2OUTRA5/MCLR/VPPVSSAVSSRB0/INT/CCP1(1)RB1/SDI/SDARB2/SDO/RX/DTRB3/PGM/CCP1(1)123420191817RA1/AN1RA0/AN0RA7/OSC1/CLKIRA6/OSC2/CLKOVDDAVDDRB7/PGD/T1OSIRB6/PGC/T1OSO/T1CKIRB5/SS/TX/CKRB4/SCK/SCL56710PIC16F87161514131211Note1:Location of CCP1 function is determined by CCPMX.FIGURE 2-3:PIC16F87 28-PIN QFN RA4/T0CKI/C2OUTRA3/AN3/C1OUTRA2/AN2/CVREFRA1/AN124RA0/AN023NC28272625RA5/MCLR/VPPNCVSSNCAVSSNCRB0/INT/CCP1(1)2221201912345671011121314NCRA7/OSC1/CLKIRA6/OSC2/CLKOVDDNCAVDDRB7/PGD/T1OSIRB6/PGC/T1OSO/T1CKIPIC16F8718171615RB2/SDO/RX/DTRB4/SCK/SCLRB1/SDI/SDARB5/SS/TX/CKNCNote1:Location of CCP1 function is determined by CCPMX.DS39607B-page 2

RB3/PGM/CCP1NC(1) 2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 2-4:PIC16F88 18-PIN DIP, SOIC RA2/AN2/CVREF/VREF-RA3/AN3/VREF+/C1OUTRA4/AN4/T0CKI/C2OUTRA5/MCLR/VPPVSSRB0/INT/CCP1(1)RB1/SDI/SDARB2/SDO/RX/DTRB3/PGM/CCP1(1)123181716RA1/AN1RA0/AN0RA7/OSC1/CLKIRA6/OSC2/CLKOVDDRB7/AN6/PGD/T1OSIRB6/AN5/PGC/T1OSO/T1CKIRB5/SS/TX/CKRB4/SCK/SCLPIC16F884567151413121110Note1:Location of CCP1 function is determined by CCPMX.FIGURE 2-5:PIC16F88 20-PIN SSOP RA2/AN2/CVREF/VREF-RA3/AN3/VREF+/C1OUTRA4/AN4/T0CKI/C2OUTRA5/MCLR/VPPVSSAVSSRB0/INT/CCP1(1)RB1/SDI/SDARB2/SDO/RX/DTRB3/PGM/CCP1(1)123420191817RA1/AN1RA0/AN0RA7/OSC1/CLKIRA6/OSC2/CLKOVDDAVDDRB7/AN6/PGD/T1OSIRB6/AN5/PGC/T1OSO/T1CKIRB5/SS/TX/CKRB4/SCK/SCL56710PIC16F88161514131211Note1:Location of CCP1 function is determined by CCPMX. 2002 Microchip Technology Inc.DS39607B-page 3

PIC16F87/88

FIGURE 2-6:PIC16F88 28-PIN QFN RA4/AN4/T0CKI/C2OUTRA3/AN3/VREF+/C1OUTRA2/AN2/CVREF/VREF-NCRA1/AN1RA0/AN0NCRA5/MCLR/VPPNCVSSNCAVSSNCRB0/INT/CCP1(1)12345672827262524232221201918171615PIC16F88RA7/OSC1/CLKIRA6/OSC2/CLKOVDDNCAVDDRB7/AN6/PGD/T1OSIRB6/AN5/PGC/T1OSO/T1CKIRB1/SDI/SDARB2/SDO/RX/DTRB3/PGM/CCP1(1)NCRB4/SCK/SCLRB5/SS/TX/CKNote1:Location of CCP1 function is determined by CCPMX.TABLE 2-1:

Pin NameRB3RB6RB7MCLRVDDVSS

PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F87/88

During Programming

FunctionPGMCLOCKDATAVPPVDDVSS

Pin Type

III/OP*PP

Pin Description

Low-Voltage ICSP Programming Input if LVPConfiguration bit equals ‘1’Clock InputData Input/OutputProgram Mode SelectPower SupplyGround

Legend:I = Input, O = Output, P = Power

*To activate the Programming mode, high voltage needs to be applied to the MCLR input. Since MCLR is used for a level source, this means that MCLR does not draw any significant current.

DS39607B-page 4

NC1011121314 2002 Microchip Technology Inc.

PIC16F87/88

3.0

3.1

PROGRAM MODE ENTRY

User Program Memory Map

3.2Data EEPROM Memory

The user memory space extends from 0x0000 to0x1FFF (8K), of which 4K (0000h-0FFFh) is physicallyimplemented. In Programming mode, the programmemory space extends from 0x0000 to 0x3FFF, withthe first half (0x0000-0x1FFF) being user programmemory and the second half (0x2000-0x3FFF) beingconfiguration memory. The PC will increment from0x0000 to 0x0FFF, then increment to 0x1000 andaccess 0x0000. Once the PC reaches 0x1FFF, it willincrement to 0x2000. From 0x2000, the PC willincrement up to 0x3FFF and wrap around to 0x2000(not to 0x0000). Once in configuration memory, thehighest bit of the PC stays a ‘1’, always pointing to theconfiguration memory. The only way to point to userprogram memory is to reset the part and re-enterProgram mode, as described in Section3.4 “ProgramMode”.

DevicePIC16F87PIC16F88

Program Flash

4K4K

The EEPROM data memory space is a separate blockof high-endurance memory that the user accessesusing a special sequence of instructions. The amountof data EEPROM memory depends on the device andis shown below in number-of-bytes.

DevicePIC16F87PIC16F88

# of Bytes

256256

The contents of data EEPROM memory have thecapability to be embedded into the HEX file.

The programmer should be able to read data EEPROMinformation from a HEX file and conversely (as anoption) write data EEPROM contents to a HEX file,along with program memory information andconfiguration bit information.

The 256 data memory locations are logically mappedand use PC<7:0>. The format for data memory storageis one data byte per address location, LSb aligned.

In the configuration memory space, 0x2000-0x201Fare physically implemented. However, only locations0x2000 through 0x2008 are available. Other locationsare reserved. Locations beyond 0x201F will physicallyaccess user memory (see Figure3-1).

 2002 Microchip Technology Inc.DS39607B-page 5

PIC16F87/88

3.3

ID Locations

A user may store identification information (ID) in fourID locations. The ID locations are mapped in[0x2000:0x2003]. It is recommended that the user useonly the four Least Significant bits of each ID location.In some devices, the ID locations read out in anunscrambled fashion once code-protection is enabled.

For these devices, it is recommended that ID locationbe written as “11 1111 1000 bbbb”, where ‘bbbb’ isID information.

In other devices, the ID locations read out normally,even after code protection. To understand how thedevices behave, refer to Table6-1.

FIGURE 3-1:PROGRAM MEMORY MAPPING

4K words

0h

2000h2001h2002h2003h2004h2005h2006h2007h2008h

ID LocationID LocationID LocationID LocationReservedReservedDevice IDConfiguration Word 1

1FFFhFFFh

Implemented

Accesses0x0000 to0x0FFF

Configuration Word 2

2009hReserved

3FFFh

DS39607B-page 6 2002 Microchip Technology Inc.

PIC16F87/88

3.4

Program Mode

program one row.

The address and program counter are reset to 0x0000by resetting the device (taking MCLR below VIL) andre-entering Programming mode. Program andconfiguration memory may then be read or verifiedusing the ‘Read Data’ and ‘Increment Address’commands.

Program mode is entered by holding pins RB6 and RB7low, while raising MCLR pin from VIL to VIHH (highvoltage). In this mode, the state of the RB3 pin does noteffect programming. Low-Voltage ICSP Programmingmode is entered by raising RB3 from VIL to VDD, andthen applying VDD to MCLR. Once in this mode, theuser program memory, as well as the configurationmemory, can be accessed and programmed in serialfashion. The mode of operation is serial, and thememory accessed is the user program memory. RB6and RB7 are Schmitt Trigger inputs in this mode.Note:

The Osc must not have 72osc clockswhile the device MCLR is between VIL andVIHH.

3.4.1

LOW-VOLTAGE ICSP PROGRAMMING MODE

Low-voltage ICSP Programming mode allows aPIC16F87/88 device to be programmed using VDDonly. However, when this mode is enabled by aconfiguration bit (LVP), the PIC16F87/88 devicededicates RB3 to control entry/exit into Programmingmode.

When the LVP bit is set to ‘1’, the Low-voltage ICSPProgramming entry is enabled. Since the LVPconfiguration bit allows Low-voltage ICSPProgramming entry in its erased state, an eraseddevice will have the LVP bit enabled at the factory.While LVP is ‘1’, RB3 is dedicated to Low-voltage ICSPProgramming. The following LVP steps assume theLVP bit is set in the Configuration register.1.2.3.4.

Apply VDD to the VDD pin.Drive MCLR low.

Apply VDD to the RB3/PGM pin.Apply VDD to the MCLR pin.

The sequence that enters the device into theProgramming mode places all other logic into theRESET state (the MCLR pin was initially at VIL). Thismeans all I/O are in the RESET state (high-impedanceinputs).Note:

The MCLR pin should be raised frombelow VIL to above the minimum VIHH(VPP), within 250µs of VDD rise. Thisensures that the device always entersProgramming mode before anyinstructions that may be in programmemory can be executed. Otherwise,unintended instruction execution couldoccur when the INTRC clock source isconfigured as the primary clock. Refer toFigure7-1.

All other specifications for High-voltage ICSP apply.To disable Low-voltage ICSP mode, the LVP bit mustbe programmed to ‘0’. This must be done while enteredwith the High-voltage Entry mode (LVP bit = 1). RB3 isnow a general purpose I/O pin.

A device RESET will clear the PC and set the addressto ‘0’. The ‘Increment Address’ command willincrement the PC. The ‘Load Configuration’ commandwill set the PC to 0x2000. The available commands areshown in Table3-1.

The normal sequence for programming four programmemory words at a time is as follows:1.2.3.4.5.6.7.8.9.10.11.12.13.

Set pointer to row location.

Issue a ‘Begin Erase’ command.Wait tprog2.

Issue an ‘End Programming’ command.

Load a word at the current program memoryaddress using the ‘Load Data’ command. Issue an ‘Increment Address’ command.

Load a word at the current program memoryaddress using the ‘Load Data’ command.Repeat Step6 and Step7 two times.

Issue a ‘Begin Programming’ command to beginprogramming. Wait tprog1.

Issue an ‘End Programming’ command.Increment to the next address.

Repeat steps 5 through 12 seven times to

 2002 Microchip Technology Inc.DS39607B-page 7

PIC16F87/88

3.4.2

SERIAL PROGRAM OPERATION

3.4.2.3

Load Data for Data Memory

The RB6 pin is used as a clock input pin, while the RB7pin is used to enter command bits, and input or outputdata during serial operation. To input a command, theclock pin (RB6) is cycled six times. Each command bitis latched on the falling edge of the clock, with the LeastSignificant bit (LSb) of the command being input first.The data on RB7 is required to have a minimum setup(tset1) and hold (thold1) time (see AC/DCspecifications), with respect to the falling edge of theclock. Commands with associated data (read and load)are specified to have a minimum delay (tdly1) of 1µsbetween the command and the data. After this delay,the clock pin is cycled 16 times, with the first cyclebeing a Start bit (0) and the last cycle being a Stop bit(0). Data is transferred LSb first.

During a read operation, the LSb will be transmittedonto RB7 on the rising edge of the second cycle, while,during a load operation, the LSb will be latched on thefalling edge of the second cycle. A minimum 1µs delay(tdly2) is specified between consecutive commands.All commands and data words are transmitted LSb first.The data is transmitted on the rising edge and latchedon the falling edge of the clock. To allow decoding ofcommands and reversal of data pin configuration, atime separation of at least 1µs (tdly1) is requiredbetween a command and a data word, or anothercommand.

The available commands are described in the followingparagraphs and listed in Table3-1.

After receiving this command, the chip will load a 14-bit“data word” when 16 cycles are applied. However, thedata memory is only 8 bits wide and, thus, only the first8 bits of data after the Start bit will be programmed intothe data memory (8 data bits and 6 zeros). It is stillnecessary to cycle the clock the full 16 cycles in orderto allow the internal circuitry to reset properly. The datamemory contains up to 256 bytes. If the device is codeprotected, the data is read as all zeros. A timingdiagram for this command is shown in Figure7-2.

3.4.2.4Read Data from Program Memory

After receiving this command, the chip will transmitdata bits out of the program memory (user orconfiguration) currently accessed, starting with thesecond rising edge of the clock input. The RB7 pin willgo into Output mode on the second rising clock edge,reverting to Input mode (high-impedance) after the 16thrising edge. A timing diagram of this command isshown in Figure7-3.

3.4.2.5Read Data from Data Memory

3.4.2.1Load Configuration

After receiving this command, the chip will transmitdata bits out of the data memory, starting with thesecond rising edge of the clock input. The RB7 pin willgo into Output mode on the second rising edge,reverting to Input mode (high-impedance) after the 16thrising edge. As previously stated, the data memory is8-bits wide and, therefore, only the first 8 bits that areoutput are actual data. A timing diagram for thiscommand is shown in Figure7-4.

Upon receipt of the Load Configuration command, thePC will be set to 0x2000 and the data sent with thecommand is discarded. The four ID locations and theconfiguration words can then be programmed using thenormal programming sequence, as described inSection3.4 “Program Mode”. A description of thememory mapping schemes of the program memory fornormal operation and Configuration mode operation isshown in Figure3-1. Once the configuration memory isentered, the only way to get back to the user programmemory is to exit the Program/Verify Test mode bytaking MCLR low (VIL).

3.4.2.6Increment Address

The PC is incremented when this command isreceived. A timing diagram of this command is shownin Figure7-5. Note:

Upon entering Programming mode, a“Load Data for Program Memory” or “LoadData for Data Memory” command of 0x01must be given before a Begin Erase orBegin Programming command is initiated.This will ensure that the programmingpointer is pointing to the correct location indata or program memory.

3.4.2.2Load Data for Program Memory

After receiving this command, the chip will load oneword (with 14 bits as a “data word”) to be programmedinto user program memory when 16 cycles are applied.A timing diagram for this command is shown inFigure7-1.

DS39607B-page 8 2002 Microchip Technology Inc.

PIC16F87/88

3.4.2.7

Begin Erase (Program and Data Memory)

The erase block size for program memory is 32 words(row) and 1 word for data memory. The row or word tobe programmed must first be erased. This is done bysetting the pointer to a location in the row or word andthen performing a ‘Begin Erase’ command. The row orword is then erased. The user must allow the combinedtime for row erase and programming, as specified inthe electrical specifications, for programming tocomplete. This is an externally timed event.

The internal timer is not used for this command, so the‘End Programming’ command must be used to stoperase.

Note1:The code-protect bits cannot be erased

with this command.

2:All ‘Begin Erase’ operations can take

place over the entire VDD range.

A timing diagram for this command is shown inFigure7-6.

The internal timer is not used for this command, so the‘End Programming’ command must be used to stopprogramming.1.2.

If the address is pointing to user memory, theuser memory alone will be affected.

If the address is pointing to the physicallyimplemented configuration memory (2000h-2008h), the configuration memory will bewritten. The configuration words will not bewritten unless the address is specificallypointing to the corresponding address.

A timing diagram for this command is shown inFigure7-7.

3.4.2.9End Programming

After receiving this command, the chip stopsprogramming the memory (configuration memory oruser program memory) that it was programming at thetime. Note:

This command will also set the write datashift latches to all ‘1’s to avoid issues withdownloading only one word before thewrite.

3.4.2.8Begin Programming Only

Programming of program and data memory will beginonce this command is received and decoded. Theuser must allow the time for programming, as specifiedin the electrical specifications, for programming tocomplete. An ‘End Programming’ command isrequired.

TABLE 3-1:COMMAND MAPPING FOR PIC16F87/88

Mapping (MSB … LSB)000001001001

000011111000

001100001011

010100011101

000000111111

externally timedexternally timedexternally timedexternally timedinternally timed0, zeroes (6), data (8), 00, zeroes (6), data (8), 0

Data0, data (14), 0 0, data (14), 0 0, data (14), 0

Voltage Range2.0V-5.5V2.0V-5.5V2.0V-5.5V2.0V-5.5V2.0V-5.5V2.0V-5.5V4.5V-5.5V4.5V-5.5V4.5V-5.5V2.0V-5.5V2.0V-5.5V

Command

Load Configuration

Load Data for Program MemoryRead Data from Program MemoryIncrement AddressBegin Erase

Begin Programming Only CycleBulk Erase Program Memory Bulk Erase Data Memory Chip Erase

Load Data for Data MemoryRead Data from Data MemoryEnd Programming

 2002 Microchip Technology Inc.DS39607B-page 9

PIC16F87/88

3.5

Erasing Program and Data Memory

3.5.1.3

Chip Erase

This command, when performed, will erase theprogram memory, EE data memory, and all of the codeprotection bits. All on-chip Flash and EEPROMmemory is erased, regardless of the address containedin the PC.

When a Chip Erase command is issued and the PCpoints to (0000h-1FFFh), the configuration words(2007h and 2008h) and the user program memory willbe erased. When a Chip Erase command is issued andthe PC points to (2000h-2008h), all of the configurationmemory, program memory, and data memory will beerased.

The Chip Erase is internally self-timed to ensure that allprogram and data memory are erased before the codeprotect bits are erased. A timing diagram for thiscommand is shown in Figure7-10. Note:

The Chip Erase operation must take placeat the 4.5V to 5.5V VDD range.

Depending on the state of the code protection bits,program and data memory will be erased usingdifferent methods. The first two commands are usedwhen both program and data memories are not codeprotected. The third command is used when eithermemory is code protected, or if you want to also erasethe code protect bits. A device programmer shoulddetermine the state of the code protection bits and thenapply the proper command to erase the desiredmemory.

3.5.1

ERASING PROGRAM AND DATA MEMORY

When both program and data memories are not code-protected, they can be individually erased by thefollowing ‘Bulk Erase’ commands. If it is desired toerase both program and data memory with a singlecommand, the ‘Chip Erase’ command must be usedwhether code protection is disabled or enabled(detailed in Section3.5.1.3 “Chip Erase”).

3.5.2

ERASING CODE-PROTECTED MEMORY

3.5.1.1Bulk Erase Program Memory

When this command is performed, and is followed bya ‘Begin Erase’ command, the entire program memorywill be erased.

If the address is pointing to user memory, only the usermemory will be erased.

If the address is pointing to the configuration memory(2000h-2008h), then both the user memory and theconfiguration memory will be erased. The configurationwords will not be erased, even if the address is pointingto location 2007h.

Previously, a load data with 0FFh command wasrecommended before any ‘Bulk Erase’. On thesedevices, this will not be required.

The ‘Bulk Erase’ command is disabled when the CPbit is programmed to ‘0’, enabling code-protect.A timing diagram for this command is shown inFigure7-8.

For the PIC16F87/88 devices, once code protection isenabled, all protected program and data memorylocations read all '0's and further programming isdisabled. The ID locations and configuration wordsread out unscrambled and can be reprogrammednormally. The only command to erase a code-protectedPIC16F87/88 device is the ‘Chip Erase’. This erasesprogram memory, data memory, configuration bits andID locations, as described in Section3.5.1.3 “ChipErase”. Since all data within the program and datamemory will be erased when this command isexecuted, the security of the data or code is notcompromised.

3.5.1.2Bulk Erase Data Memory

When this command is performed, and is followed bya ‘Begin Erase’ command, the entire data memory willbe erased.

The ‘Bulk Erase Data’ command is disabled when theCPD bit is programmed to ‘0’, enabling protected datamemory. A timing diagram for this command is shownin Figure7-9. Note:

All ‘Bulk Erase’ operations must take placeat the 4.5V to 5.5V VDD range.

DS39607B-page 10 2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 3-2:ALGORITHM 1 FLOW CHART – PROGRAM MEMORY (2.0V ≤ VDD < 5.5V) StartSet VDD = VDDPBeginEraseCommandWait tprog2EndProgrammingCommandLoad DataCommandIncrementAddressCommandNoFour LoadsDone?YesBeginProgramming OnlyCommandWait tprog1EndProgrammingCommandVerify allLocationsIncrementAddressCommandNoAllRow LocationsDone?YesReport VerifyErrorNoData Correct?YesEndIncrementAddressCommandNoAll LocationsDone?Yes 2002 Microchip Technology Inc.DS39607B-page 11

PIC16F87/88

FIGURE 3-3:ALGORITHM 2 FLOW CHART – PROGRAM MEMORY (4.5V ≤ VDD ≤ 5.5V)StartChip EraseSequenceSet VDD = VDDPLoad DataCommandIncrementAddressCommandNoFour LoadsDone?YesBeginProgramming OnlyCommandWait tprog1EndProgrammingCommandIncrementAddressCommandNoAll LocationsDone?YesVerify allLocationsReport VerifyErrorNoData Correct?YesEndDS39607B-page 12 2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 3-4:

FLOW CHART – PIC16F87/88 CONFIGURATION MEMORY (2.0V ≤ VDD < 5.5V) AND (4.5V ≤ VDD < 5.5V)

PROGRAM

FOURLOCATIONS

StartBeginEraseCommandStart

LoadConfigurationData(Set PC = 2000h)LoadConfigurationDataWait tprog2

Program IDLocation?NoYesProgram FourLocationsRead Data CommandEnd

ProgrammingCommand

ReportProgrammingFailureNoData Correct?YesAddress = 0x2003?NoIncrementAddressCommandLoad DataCommand

IncrementAddressCommand

NoFour LoadsDone?

YesIncrementAddressCommandAddress = 0x2004?YesIncrementAddressCommandYesBeginProgram OnlyCommand

NoWait tprog1

End

ProgrammingCommand

End

IncrementAddressCommandPROGRAMCONFIG1andCONFIG2

IncrementAddressCommandStart

IncrementAddressCommandLoad DataCommand

ProgramConfig1BeginProgram OnlyCommand

Report ProgramConfigurationWord ErrorNoData Correct?YesRead Data CommandProgramConfig2Wait tprog1

End

ProgrammingCommand

EndEnd

 2002 Microchip Technology Inc.DS39607B-page 13

PIC16F87/88

4.0

CONFIGURATION WORD

The PIC16F87/88 has several configuration bits.These bits can be written to ‘0’ or ‘1’ with the ‘BeginProgram Only’ command. A ‘Begin Erase’ command isnot required when programming configuration memory.

4.1Device ID Word

The device ID word for the PIC16F87/88 is located at2006h.

TABLE 4-1:

DevicePIC16F87PIC16F88

DEVICE ID VALUE

Device ID ValueDev00 0111 001000 0111 0110

RevXXXXXXXX

DS39607B-page 14 2002 Microchip Technology Inc.

PIC16F87/88

REGISTER 4-1:

CPbit 13bit 13

CP: Flash Program Memory Code Protection bits

CONFIGURATION WORD 1 (2007h) REGISTER

WRT0

CPD

LVP

BORENMCLREFOSC2PWRTENWDTENFOSC1FOSC0

bit 0

CCPMXDEBUGWRT1

1 = Code protection off

0 = 0000h to 0FFFh code protected (all protected)

bit 12

CCPMX: CCP Mux bit1 = CCP1 function on RB00 = CCP1 function on RB3

DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debuggerWRT1:WRT0: Flash Program Memory Write Enable bits

11 = Write protection off

10 = 0000h to 00FFh write-protected, 0100h to 0FFFh may be modified by EECON control01 = 0000h to 07FFh write-protected, 0800h to 0FFFh may be modified by EECON control00 = 0000h to 0FFFh write-protected

bit 11

bit 10-9

bit 8CPD: Data EE Memory Code Protection bit

1 = Code protection off

0 = Data EE memory code-protected

bit 7

LVP: Low-voltage Programming Enable bit

1 = RB3/PGM pin has PGM function, Low-voltage Programming enabled0 = RB3 is digital I/O, HV on MCLR must be used for programming

bit 6

BOREN: Brown-out Reset Enable bit

1 = BOR enabled0 = BOR disabled

bit 5

MCLRE: RA5/MCLR Pin Function Select bit

1 = RA5/MCLR pin function is MCLR0 = RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD

bit 3

PWRTEN: Power-up Timer Enable bit

1 = PWRT disabled0 = PWRT enabled

bit 2

WDTEN: Watchdog Timer Enable bit

1 = WDT enabled0 = WDT disabled

bit 4, 1-0FOSC2:FOSC0: Oscillator Selection bits

111 = EXTRC oscillator; CLKO function on RA6/OSC2/CLKO110 = EXTRC oscillator; port I/O function on RA6/OSC2/CLKO101 = INTRC oscillator; CLKO function on RA6/OSC2/CLKO100 = INTRC oscillator; port I/O function on RA6/OSC2/CLKO011 = EXTCLK; port I/O function on RA6/OSC2/CLKO010 = HS oscillator001 = XT oscillator000 = LP oscillator

Legend:R = Readable bit-n = Value at POR

W = Writable bit1 = bit is set

U = Unimplemented bit, read as ‘0’0 = bit is cleared

x = bit is unknown

 2002 Microchip Technology Inc.DS39607B-page 15

PIC16F87/88

REGISTER 4-2:

U-1—bit 13bit 13-2bit 1

U-1—

U-1—

CONFIGURATION WORD 2 (2008h) REGISTER

U-1—

U-1—

U-1—

U-1—

U-1—

U-1—

U-1—

U-1—

U-1—

IESO

FCMEN

bit 0

Unimplemented: Read as ‘1’

IESO: Internal External Switch Over bit

1 = Internal External Switch Over mode enabled0 = Internal External Switch Over mode disabled

FCMEN: Fail-Safe Clock Monitor Enable bit

bit 0

1 = Fail-Safe Clock Monitor enabled0 = Fail-Safe Clock Monitor disabled

Legend:R = Readable bit-n = Value at POR

W = Writable bit

U = Unimplemented bit, read as ‘0’

1 = bit is set0 = bit is clearedx = bit is unknown

DS39607B-page 16 2002 Microchip Technology Inc.

PIC16F87/88

5.0

EMBEDDING CONFIGURATION WORD AND ID INFORMATION IN HEX FILE

To allow portability of code, the programmer is required to read the configuration word and ID locations from the HEXfile when loading the HEX file. If configuration word information was not present in the HEX file, a simple warning

=message may be issued. Similarly, while saving a HEX file, configuration word and ID information must be included.

An option to not include this information may be provided.

Specifically for the PIC16F87/88, the EEPROM data memory should also be embedded in the HEX file (seeSection3.2 “Data EEPROM Memory”).

Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

6.0CHECKSUM COMPUTATION

Checksum is calculated by reading the contents of thePIC16F87/88 memory locations and totaling theopcodes, up to the maximum user-addressablelocation (e.g., 0xFFF for the PIC16F87/88). Any carrybits exceeding 16 bits are neglected. Finally, theconfiguration word (appropriately masked) is added tothe checksum. Checksum computation for eachmember of the PIC16F87/88 devices is shown inTable6-1.

The checksum is calculated by summing the following:•The contents of all program memory locations•The configuration words, appropriately masked•Masked ID locations (when applicable)

The Least Significant 16 bits of this sum are thechecksum.

The following table describes how to calculate thechecksum for each device. Note that the checksumcalculation differs depending on the code protectsetting. Since the program memory locations read outdifferently depending on the code protect setting, thetable describes how to manipulate the actual programmemory values to simulate the values that would beread from a protected device. When calculating achecksum by reading a device, the entire programmemory can simply be read and summed. Theconfiguration words and ID locations can always beread.

Note that some older devices have an additional valueadded in the checksum. This is to maintain compatibilitywith older device programmer checksums.

TABLE 6-1:

DevicePIC16F87PIC16F88

CHECKSUM COMPUTATION

Code-ProtectOFFONOFFON

Checksum*

SUM(0000:0FFF) + (CONFIG0 & 3FFF) + (CONFIG1 & 0003)(CONFIG0 & 3FFF) + (CONFIG1 & 0003) + SUM_ID

SUM(0000:0FFF) + (CONFIG0 & 3FFF) + (CONFIG1 & 0003)(CONFIG0 & 3FFF) + (CONFIG1 & 0003) + SUM_ID

Blank Value3002500430025004

0x25E6 at 0and MaxAddressFBD0IBD2FBD0IBD2

Legend:CFGW=Configuration Word

SUM[a:b]=[Sum of locations a to b inclusive]

SUM_ID=ID locations masked by 0xF, then made into a 16-bit value with ID0 as the Most Significant

nibble.

For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234. *Checksum=[Sum of all the individual expressions] MODULO [0xFFFF] + Addition &=Bitwise AND

 2002 Microchip Technology Inc.DS39607B-page 17

PIC16F87/88

7.0

PROGRAM MODE ELECTRICAL CHARACTERISTICS

TIMING REQUIREMENTS FOR PROGRAM MODE

Standard Operating Procedure (unless otherwise stated)Operating Temperature0 ≤ TA ≤ +70°COperating Voltage2.0V ≤ VDD ≤ 5.5VSym

Min

Typ

Max

Units

Conditions/Comments

TABLE 7-1:

AC/DC CHARACTERISTICS

POWER SUPPLY PINS

Characteristics

General

VDD level for Begin Erase, Begin Program operations and EECON1 writes of program memoryVDD level for Begin Erase, Begin Program operations and EECON1 writes of data memory

VDD2.0—5.5V

VDD2.0—5.5V

VDD level for Bulk Erase, Chip Erase, VDDand Begin Program operations of program and data memory

Begin Programming Only cycle timeBegin Erase

Bulk Erase cycle timeChip Erase cycle time

High voltage on MCLR and

RA4/T0CKI for Program mode entryMCLR rise time (VSS to VHH) for Program mode entry(RB6, RB7) input high level(RB6, RB7) input low level

RB<7:4> setup time before MCLR↑ (Program mode selection pattern setup time)

RB<7:4> hold time after MCLR↑ (Program mode selection pattern setup time)Serial Program

Data in setup time before clock↓Data in hold time after clock↓Data input not driven to next clock input (delay required between command/data or command/command)

Delay between clock↓ to clock↑ of next command or dataClock↑ to data out valid (during read data)

Setup time between VDD rise and MCLR rise

tset1 thld1 tdly1 tprog1 tprog2 tprog3 tprog4 VIHH tVHHR VIH1 VIL1 tset0

4.5—5.5V

121228VDD + 3.5

—0.8VDD0.2VDD100

———————————

——————13.51.0———

msmsmsmsmsmsVµsVVns

Externally Timed, > 4.5VExternally Timed, < 4.5VExternally Timed, > 4.5VExternally Timed, < 4.5VExternally TimedInternally Timed

Schmitt Trigger inputSchmitt Trigger input

thld05——µs

1001001.0100

————

————

nsnsµsns

2.0V ≤ VDD < 4.5V4.5V ≤ VDD ≤ 5.5V

tdly2tdly3tpu

1.010080 tset0

————

———250

µsnsnsµs

2.0V ≤ VDD < 4.5V4.5V ≤ VDD ≤ 5.5V

DS39607B-page 18 2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 7-1:

VIHH

MCLRtset0

LOAD DATA FOR USER PROGRAM MEMORY COMMAND (PROGRAM)

(Clock)

󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁RB6󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁RB7󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁1 µs min

1

2

3

4

5

6

tdly2

1

2

3

4

5

15

16thld0

0

1

0tset1thld1

}}0

0

X

tdly1

1 µs min

}}strt_bittset1thld1

stp_bit(Data)

100 ns min

Reset

Program Mode

100 ns min

FIGURE 7-2:

VIHH

MCLRRB6(Clock)

LOAD DATA FOR USER DATA MEMORY COMMAND (PROGRAM)

1 µs min

1

2

3

4

5

6

tdly2

1

2

3

4

5

15

16󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁tset0

󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁thld0

1

1

0tset1thld1

}}0

0

X

tdly1

1 µs min

}}strt_bit

stp_bitRB7(Data)

tset1thld1

100 ns min

Reset

Program Mode

100 ns min

FIGURE 7-3:

VIHH

MCLRREAD DATA FROM PROGRAM MEMORY COMMAND (PROGRAM)

󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁RB6󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁(Clock)󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁RB7󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁(Data)

tset0

tdly2

thld01

2

3

4

5

6

1 µs min

1

2

3tdly3

0tset1

thld1

100 ns min}}RB7 = Input

0

1

0

0

X

tdly11 µs min

RB7 = Output

RB7Inputbit 0

bit 13

4

5

15

16Reset

Program Mode

 2002 Microchip Technology Inc.DS39607B-page 19

PIC16F87/88

FIGURE 7-4:

VIHH

MCLRtset0

tdly2

thld01234561 µs min

1

2

3tdly3

1tset1

thld1

100 ns min}}01

0

0

X

tdly11 µs min

RB7 = Input

RB7 = Output

RB7Inputbit 0

bit 13

READ DATA FROM DATA MEMORY COMMAND (PROGRAM)

󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁RB6󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁(Clock)󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁RB7󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁󰀁(Data)

451516Reset

Program Mode

FIGURE 7-5:

MCLR

INCREMENT ADDRESS COMMAND (SERIAL PROGRAM)

VIHH

tdly2

1

2

3

4

5

6

1 µs min.

1

Next Command

2

RB6(Clock)

RB7(Data)

011tset1

0XX

tdly1

X0

thld1

100 ns min.

Reset

Program Mode

}}1 µs min.

FIGURE 7-6:

VIHH

MCLRBEGIN ERASE (SERIAL PROGRAM)

tprog2

1

2

3

4

5

6

1

End Programming Command

2

RB6(Clock)

RB7(Data)

000tset1

10X

?

X0

thld1

100 ns min.

Reset

Program Mode

}}DS39607B-page 20 2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 7-7:

MCLR1RB6(Clock)

23456BEGIN PROGRAMING ONLY COMMAND (SERIAL PROGRAM)

VIHH

tprog1

1

End Programming Command

2

RB7(Data)

000tset1

11X

?

X0

thld1

100 ns min.

Reset

Program Mode

}}FIGURE 7-8:

VIHH

MCLR

BULK ERASE PROGRAM MEMORY COMMAND (SERIAL PROGRAM/VERIFY)

tprog3

1

End

Programming

2

Begin Erase

1

RB6(Clock)

2

3

4

5

6

1

2

RB7(Data)

100tset1

1XXX0

?

X0

thld1

100 ns min.

Reset

Program/Verify Test Mode

}}FIGURE 7-9:

VIHH

MCLRBULK ERASE DATA MEMORY COMMAND (SERIAL PROGRAM/VERIFY)

tprog3

1

Begin Erase

1RB6(Clock)

234561

2

End Programming

2

RB7(Data)

110tset1

1XXX0

?

X0

thld1

100 ns min.

Reset

Program/Verify Test Mode

}} 2002 Microchip Technology Inc.DS39607B-page 21

PIC16F87/88

FIGURE 7-10:

MCLR

1

RB6(Clock)

2

3

4

5

6

CHIP ERASE COMMAND (SERIAL PROGRAM)

VIHH

tprog4

Next Command1

2

RB7(Data)

111tset1

1XX

tdly11 µs min.X0

thld1

100 ns min.

Reset

Program Mode

}}FIGURE 7-11:

MCLR

PROGRAM MODE ENTRY

VIHH

VDD

tpu

1

RB6(CLOCK)

2

3

4

5

RB7(DATA)

Reset

Program Mode

DS39607B-page 22 2002 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:•••

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

••

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is intended through suggestion onlyand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.No representation or warranty is given and no liability isassumed by Microchip Technology Incorporated with respectto the accuracy or use of such information, or infringement ofpatents or other intellectual property rights arising from suchuse or otherwise. Use of Microchip’s products as critical com-ponents in life support systems is not authorized except withexpress written approval by Microchip. No licenses are con-veyed, implicitly or otherwise, under any intellectual propertyrights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,

PROMATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense,

FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A.All other trademarks mentioned herein are property of their respective companies.

© 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003 . The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

DS39607B-page 23 2003 Microchip Technology Inc.

M

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DS39607B-page 24 2002 Microchip Technology Inc.