P4C1256-45DILF资料

HIGH SPEED 32K x 8STATIC CMOS RAM

FEATURES

High Speed (Equal Access and Cycle Times)— 12/15/20/25/35 ns (Commercial)— 15/20/25/35/45 ns (Industrial)— 20/25/35/45/55/70 ns (Military)Low Power

Single 5V±10% Power Supply

Easy Memory Expansion Using CE and OEInputs

Common Data I/OThree-State Outputs

Fully TTL Compatible Inputs and OutputsAdvanced CMOS TechnologyFast tOE

Automatic Power DownPackages

—28-Pin 300 mil DIP, SOJ, TSOP—28-Pin 300 mil Ceramic DIP—28-Pin 600 mil Ceramic DIP—28-Pin CERPACK—28-Pin SOP

—28-Pin LCC (350 mil x 550 mil)—32-Pin LCC (450 mil x 550 mil)

DESCRIPTION

The P4C1256 is a 262,144-bit high-speed CMOSstatic RAM organized as 32Kx8. The CMOS memoryrequires no clocks or refreshing, and has equal accessand cycle times. Inputs are fully TTL-compatible. TheRAM operates from a single 5V±10% tolerance powersupply.

Access times as fast as 12 nanoseconds permit greatlyenhanced system operating speeds. CMOS is utilizedto reduce power consumption to a low level. TheP4C1256 is a member of a family of PACE RAM™ prod-ucts offering fast access times.

The P4C1256 device provides asynchronous operationwith matching access and cycle times. Memory loca-tions are specified on address pins A0 to A14. Readingis accomplished by device selection (CE and outputenabling (OE) while write enable (WE) remains HIGH.By presenting the address under these conditions, thedata in the addressed memory location is presented onthe data input/output pins. The input/output pins stayin the HIGH Z state when either CE or OE is HIGH orWE is LOW.

Package options for the P4C1256 include 28-pin 300mil DIP, SOJ and TSOP packages. For military tempera-ture range, Ceramic DIP and LCC packages are avail-able.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)CERPACK (F4) SIMILAR1519BSee end of datasheet for LCC and TSOPpin configurations.Document # SRAM119 REV G

1

Revised June 2007

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P4C1256

MAXIMUM RATINGS(1)

SymbolVCC

ParameterPower Supply Pin withRespect to GNDTerminal Voltage withRespect to GND(up to 7.0V)

Operating Temperature

Value–0.5 to +7–0.5 toVCC +0.5–55 to +125

Unit VSymbolTBIASTSTGPTIOUT

ParameterTemperature UnderBias

Storage TemperaturePower DissipationDC Output Current

Value–55 to +125–65 to +150

1.050

Unit°C°CWmA

VTERMTA

V°C

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Grade(2)Military

AmbientTemperature

GND0V0V0V

VCC

5.0V ± 10%5.0V ± 10%5.0V ± 10%

CAPACITANCES(4)

VCC = 5.0V, TA = 25°C, f = 1.0MHzSymbolCINCOUT

ParameterInput Capacitance

ConditionsTyp.UnitVIN = 0V

810

pFpF

–55°C to +125°C–40°C to +85°CIndustrial

Commercial0°C to +70°C

Output CapacitanceVOUT = 0V

DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage(2)SymbolVIHVILVHCVLCVOLVOH

Parameter

Input High VoltageInput Low VoltageCMOS Input High VoltageCMOS Input Low VoltageOutput Low Voltage

(TTL Load)

Output High Voltage(TTL Load)

Input Leakage Current

IOL = +8 mA, VCC = Min.IOH = –4 mA, VCC = Min.VCC = Max. Mil.VIN = GND to VCC Ind./Com’l.VCC = Max., Mil.

ILO

Output Leakage Current

CE = VIH, Ind./Com’l.VOUT = GND to VCC

CE ≥ VIH Mil.

ISB

Standby Power SupplyVCC= Max, Ind./Com’l.Current (TTL Input Levels)f = Max., Outputs Open

______

4530

______

30n/a

mA

2.4–10–5–10–5

+10+5+10+5

Test Conditions

P4C1256MinMax

VCC +0.52.2

P4C1256LUnit

MinMax

VCC +0.5V2.2

VVVVV

+5n/a+5n/a

µAµA

0.80.8–0.5(3)–0.5(3)

VCC –0.2VCC +0.5VCC –0.2VCC +0.5–0.5(3)

0.20.4

2.4–5n/a–5n/a–0.5(3)

0.20.4

ILI

CE ≥ VHC Mil.

ISB1

Standby Power SupplyCurrent

(CMOS Input Levels)

VCC= Max, Ind./Com’l.f = 0, Outputs OpenVIN ≤ VLC or VIN ≥ VHC

______

2010

______

10n/a

mA

N/A = Not Applicable

Document # SRAM119 REV GPage 2 of 17

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P4C1256DATA RETENTION CHARACTERISTICS (P4C1256L Military Temperature Only)

SymbolVDRICCDRtCDRtR†

*TA = +25°C

§tRC = Read Cycle Time

†

Parameter

VCC for Data RetentionData Retention CurrentChip Deselect toData Retention TimeOperation Recovery Time

Test ConditonsMin2.0

Typ.*VCC = 2.0V 3.0VMaxVCC = 2.0V 3.0V

UnitV

CE ≥ VCC –0.2V,VIN ≥ VCC –0.2Vor VIN ≤ 0.2V

0tRC§

1015100200µAnsns

This parameter is guaranteed but not tested.

DATA RETENTION WAVEFORM

POWER DISSIPATION CHARACTERISTICS VS. SPEED

Symbol

Parameter

Temperature

RangeCommercialMilitary

–12170N/AN/A

–15160170N/A

–20155165170

–25150160165

–35145155160

–45N/A150155

–55N/AN/A150

–70N/AN/A150

UnitmAmAmA

ICC

Dynamic Operating Current*Industrial

*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.

Document # SRAM119 REV GPage 3 of 17

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P4C1256

AC ELECTRICAL CHARACTERISTICS—READ CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

Sym.tRCtAAtACtOHtLZtHZtOE

ParameterRead Cycle TimeAddress AccessTimeChip EnableAccess TimeOutput Hold fromAddress ChangeChip Enable toOutput in Low ZChip Disable toOutput in High ZOutput EnableLow to DataValid

Output EnableLow to Low ZOutput EnableHigh to High ZChip Enable toPower Up TimeChip Disable toPower DownTime

-1212

121222

55

22

-1515

1515

2287

20

-20

252020

3399

-25

352525

331110

-35

453535

331515

-45

554545

332020

-55

705555

332525

-70

MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax

Unitns

7070

nsnsnsns

3030

nsns

tOLZtOHZtPUtPD

0

50

12

0

70

15

0

90

20

0

110

20

0

150

20

0

200

25

0

250

30

0

300

35

nsnsnsns

Document # SRAM119 REV GPage 4 of 17

P4C1256TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)

TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)

TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)

Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS maycause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specificationis not implied. Exposure to MAXIMUM rating conditions for extendedperiods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feet perminute of air flow.

3.Transient inputs with VIL and IIL not more negative than –3.0V and–100mA, respectively, are permissible for pulse widths up to 20 ns.

4.This parameter is sampled and not 100% tested.5.WE is HIGH for READ cycle.

6.CE is LOW and OE is LOW for READ cycle.

7.ADDRESS must be valid prior to, or coincident with CE transition LOW.8.Transition is measured ± 200 mV from steady state voltage prior tochange, with loading as specified in Figure 1. This parameter issampled and not 100% tested.

9.Read Cycle Time is measured from the last valid address to the firsttransitioning address.

Document # SRAM119 REV GPage 5 of 17

P4C1256

AC CHARACTERISTICS—WRITE CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

Sym.tWCtCW

Parameter

-12-151510

20

-20

25

-25

3522

-35

45

-45

55

-55

70

-70

MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax9

15

18

30

35

40

Unitnsns

Write Cycle Time12Chip EnableTime to End ofWrite

Address Valid toEnd of WriteAddress Set-upTime

Write PulseWidth

Address HoldTime

Data Valid toEnd of WriteDate Hold TimeWrite Enable toOutput in High ZOutput Activefrom End of Write

3

tAWtAStWPtAHtDWtDHtWZtOW

909080

7

10011090

83

150150110

103

200180130

113

250220150

155

350250200

185

400300250

250

450350300

300

nsnsnsnsnsnsnsns

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)

Document # SRAM119 REV GPage 6 of 17

P4C1256TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)

Notes:

10.CE and WE must be LOW for WRITE cycle.

11.OE is LOW for this WRITE cycle to show tWZ and tOW.

12.If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state

13.Write Cycle Time is measured from the last valid address to the first

transitioning address.

Document # SRAM119 REV GPage 7 of 17

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P4C1256

AC TEST CONDITIONS

Input Pulse LevelsGND to 3.0V

Input Rise and Fall Times3nsInput Timing Reference Level1.5VOutput Timing Reference Level1.5V

Output Load

See Figures 1 and 2

Figure 1. Output LoadDocument # SRAM119 REV GModeCEOEWEI/OPowerStandbyHXXHigh ZStandbyStandbyXXXHigh ZStandbyDOUT Disabled

LHHHigh ZActive

LLHDOUTL

X

L

High Z

ActiveFigure 2. Thevenin Equivalent

Page 8 of 17

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P4C1256ORDERING INFORMATION

SELECTION GUIDE

The P4C1256 is available in the following temperature, speed and package options. The P4C1256L is available onlyover the military temperature range. **

* Military temperature range with MIL-STD-883, Class B processing.

** For RoHS compliant plastic products, the suffix \"LF\" (Lead Free) should be added to the part number.N/A = Not Available

Document # SRAM119 REV GPage 9 of 17

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P4C1256

Temperature RangeMilitary TemperaturePackageSide Brazed DIP (300 mil)Side Brazed DIP (600 mil)Ceramic DIPCERPACKLCC (28-Pin)LCC (32-Pin)Speed12N/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/A15N/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/A20-20CM-20CWM-20DM-20FM-20L28M-20L32M-20CMB-20CWMB-20DMB-20FMB-20L28MB-20L32MB25-25CM-25CWM-25DM-25FM-25L28M-25L32M-25CMB-25CWMB-25DMB-25FMB-25L28MB-25L32MB35-35CM-35CWM-35DM-35FM-35L28M-35L32M-35CMB-35CWMB-35DMB-35FMB-35L28MB-35L32MB45-45CM-45CWM-45DM-45FM-45L28M-45L32M-45CMB-45CWMB-45DMB-45FMB-45L28MB-45L32MB55-55CM-55CWM-55DM-55FM-55L28M-55L32M-55CMB-55CWMB-55DMB-55FMB-55L28MB-55L32MB70-70CM-70CWM-70DM-70FM-70L28M-70L32M-70CMB-70CWMB-70DMB-70FMB-70L28MB-70L32MBMilitary Processed*Side Brazed DIP (300 mil)Side Brazed DIP (600 mil)Ceramic DIPCERPACKLCC (28-Pin)LCC (32-Pin)LCC PIN CONFIGURATIONS

28 LCC (L5)

32 LCC (L6)

Document # SRAM119 REV GPage 10 of 17

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P4C1256Pkg ## PinsSymbolAbb2CDEeAeLQS1S2C528 (300 mil)MinMax-0.2250.0140.0260.0450.0650.0080.018-1.4850.2400.3100.300 BSC0.100 BSC0.1250.2000.0150.0700.005-0.005-SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (300 Mils)

Document # SRAM119 REV GPage 11 of 17

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P4C1256

Pkg ## PinsSymbolAbb2CDEeAeLQS1αD5-228 (300 mil)MinMax-0.2250.0140.0260.0450.0650.0080.018-1.4850.2400.3100.300 BSC0.100 BSC0.1250.2000.0150.0600.005-0°15°CERDIP DUAL IN-LINE PACKAGE

Pkg ## PinsSymbolAbcDEekLQSS1F428MinMax0.0600.0900.0150.0220.0040.009-0.7300.3300.3800.050 BSC0.0050.0180.2500.3700.0260.045-0.0850.005-CERPACK CERAMIC FLAT PACKAGE

Document # SRAM119 REV GPage 12 of 17

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Pkg #J5# Pins28 (300 mil)SymbolMinMaxA0.1200.148A10.078-b0.0140.020C0.0070.011D0.7000.730e0.050 BSCE0.335 BSCE10.2920.300E20.267 BSCQ0.025-Pkg #L5# Pins28SymbolMinMaxA0.0600.075A10.0500.065B10.0220.028D0.3420.358D10.200 BSCD20.100 BSCD3-0.358E0.5400.560E10.400 BSCE20.200 BSCE3-0.558e0.050 BSCh0.040 REFj0.020 REFL0.0450.055L10.0450.055L20.0750.095ND5NE9Document # SRAM119 REV GP4C1256SOJ SMALL OUTLINE IC PACKAGE

RECTANGULAR LEADLESS CHIP CARRIER (28 Pins)

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P4C1256

Pkg #L6# Pins32SymbolMinMaxA0.0600.075A10.0500.065B10.0220.028D0.4420.458D10.300 BSCD20.150 BSCD3-0.458E0.5400.560E10.400 BSCE20.200 BSCE3-0.558e0.050 BSCh0.040 REFj0.020 REFL0.0450.055L10.0450.055L20.0750.095ND7NE9Pkg #P5# Pins28 (300 mil)SymbolMinMaxA-0.210A1-b0.0140.023b20.0450.070C0.0080.014D1.3451.400E10.2700.300E0.3000.380e0.100 BSCeB-0.430L0.1150.150α0°15°Document # SRAM119 REV GRECTANGULAR LEADLESS CHIP CARRIER (32 Pins)

PLASTIC DUAL IN-LINE PACKAGE

Page 14 of 17

Pkg #T1# Pins28SymbolMinMaxA0.0390.047A20.0360.040b0.0070.011D0.4610.469E0.3110.319e0.022 BSCHD0.5200.535Pkg #S11-1# Pins28 (300 Mil)SymbolMinMaxA0.0930.104A10.0040.012b20.0130.020C0.0090.012D0.6960.712e0.050 BSCE0.2910.299H0.3940.419h0.0100.029L0.0160.050α0°8°Document # SRAM119 REV GP4C1256SOIC/SOP SMALL OUTLINE IC PACKAGE

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P4C1256

SOIC/SOP SMALL OUTLINE IC PACKAGE

αDocument # SRAM119 REV GPage 16 of 17

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P4C1256REVISIONS

DOCUMENT NUMBER:DOCUMENT TITLE:REV.ORABCDEFG

ISSUEDATE1997Oct-05Oct-05Apr-06May-06Jun-06Aug-06Jun-07

SRAM119

HIGH SPEED 32K x 8 STATIC CMOS RAM

ORIG. OFCHANGERKKJDBJDBJDBJDBJDBJDBJDB

DESCRIPTION OF CHANGENew Data SheetChange logo to PyramidAdded SOP Package

Added Lead-Free ordering information.Added PDIP to Ordering Information diagramAdded Ceramic DIP packageUpdated SOJ package informationCorrected SOP package information

Document # SRAM119 REV GPage 17 of 17