AT22LV10L-25SI资料

Features

•Low Voltage Programmable Logic Device–Wide Power Supply Range - 3.0V to 5.5V–Ideal for Battery Powered Systems•High Speed Operation

–20 ns max Propagation Delay at V•CC = 3.0VCommercial and Industrial Temperature Ranges•Familiar 22V10 Logic Architecture•

Low Power 3-Volt CMOS Operation

AT22LV10L

AT22LV10TempCom./Ind.Com./Ind.ICC (mA)

4 / 5

35 / 45

VCC = 3.6V

•CMOS and TTL Compatible Inputs and Outputs

–10 µA Leakage Maximum

•Reprogrammable - Tested 100% for Programmability•High Reliability CMOS Technology

–2000V ESD Protection–200 mA Latchup Immunity

•Dual-In-Line and Surface Mount Packages

Logic Diagram

Description

The AT22LV10 and AT22LV10L are low voltage compatible CMOS high performanceProgrammable Logic Devices (PLDs). Speeds down to 20 ns and power dissipationas low as 14.4 mW are offered. All speed ranges are specified over the 3.0V to 5.5Vrange. All pins offer a low ±10 µA leakage.

(continued)Pin Configurations

DIP/SOICPLCC

Pin NameFunction

CLK/INClock and Logic InputINLogic InputsI/OBidirectional Buffers*No Internal ConnectionVCC

3.0V to 5.5V Supply

Low-Voltage UV Erasable Programmable Logic DeviceAT22LV10AT22LV10LRev. 0190C—05/981

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The AT22LV10L provides the optimum low power CMOSPLD solution, with low DC power (1 mA typical at VCC =3.3V) and full CMOS output levels. The AT22LV10L signifi-cantly reduces total system power, allowing battery pow-ered operation.

Full CMOS output levels help reduce power in many othersystem components.

The AT22LV10 and AT22LV10L logic architectures areidentical to the familiar 22V10. Each output is allocatedfrom eight to 16 product terms, which allows highly com-plex logic functions to be realized.

Two additional product terms are included to provide syn-chronous preset and asynchronous reset. These terms arecommon to all ten registers. All registers are automaticallycleared upon power up.

Register preload simplifies testing. A security fuse preventsunauthorized copying of programmed fuse patterns.

Absolute Maximum Ratings*

Temperature Under Bias................................-55°C to +125°CStorage Temperature.....................................-65°C to +150°CVoltage on Any Pin with

Respect to Ground........................................-2.0V to +7.0V (1)Voltage on Input Pins with Respect to Ground

During Programming...................................-2.0V to +14.0V (1)Programming Voltage with

Respect to Ground......................................-2.0V to +14.0V (1)Integrated UV Erase Dose.............................7258 W•sec/cm2*NOTICE:

Stresses beyond those listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi-tions beyond those indicated in the operational sec-tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Minimum voltage is -0.6V dc whihc may undershoot to -2.0V for pulses of less than 20 ns. Maximum pin voltage is VCC + 0.75V dc which may undershoot to VCC + 2.0V for pulses of less than 20 ns.

Note:1.

Logic Options

Output Options

DC and AC Operating Conditions

Commercial

Operating Temperature (Case)VCC Power Supply

0°C - 70°C3.0V to 5.5V

Industrial-40°C - 85°C3.0V to 5.5V

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AT22LV10(L)

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AT22LV10(L)

DC Characteristics

SymbolILIILO

ParameterInput Load CurrentOutput Leakage Current

Condition

VIN = -0.1V to VCC + 1VVOUT = -0.1V to VCC + 0.1V

AT22LV10

Com.Ind.Com.Ind.

20/5020/501/21/2

Min

Typ

Max101035/9045/1004/125/15-120

-0.6-0.62.0

VCC = 3.0V

VOL

Output Low VoltageVIN = VIH or VIL

VCC = 4.5VVCC = 3.0V

VOHNote:

Output High Voltage

VIN = VIH or VIL,VCC = 3.0V / 4.5V

Com.,Ind.Com.,Ind.Com.,Ind.IOH = -100 µA

IOH = -0.4 mA / -4.0 mA

IOL = 8 mA IOL = 16 mAIOL = 6 mA

VCC - 0.32.4

0.80.6VCC + 0.75

0.50.50.35

UnitsµAµAmAmAmAmAmAVVVVVVVV

ICC

Power Supply Current

VCC = 3.6V / 5.5V, VIN = GND,Outputs Open

AT22LV10L

IOS (1)VIL1VIL2VIH

Output Short Circuit Current

Input Low VoltageInput Low VoltageInput High Voltage

VOUT = 0.5V4.5V ≤ VCC ≤ 5.5V3.0V ≤ VCC < 4.5V

1.Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

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AC Characteristics for the AT22LV10

AT22LV10-20

SymboltPDtEAtERtCFtCOtStHtPtW

Parameter

Input or Feedback to Non-Registered OutputInput to Output EnableInput to Output DisableClocktoFeedbackClock to Output

Input or Feedback Setup TimeHold TimeClock PeriodClock Width

External Feedback 1/(tS+tCO)

FMAX

Internal Feedback 1/(tS + tCF)No Feedback 1/(tP)

tAWtARtAP

Asynchronous Reset WidthAsynchronous Reset, Synchronous Preset, Recovery Time

Asynchronous Reset to

Registered Output Reset

2020

1212

00100105

41.652.6100.0

2525

1515

486

Min

Typ12

Max202020914

00120126

34.547.683.3

Min

AT22LV10-25

Typ1515155107

Max252525917

Units nsnsnsnsnsnsnsnsnsMHzMHzMHz nsns

15251828ns

AC Waveforms(1)

Note:1.Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

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AT22LV10(L)

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AT22LV10(L)

AC Characteristics for the AT22LV10L

AT22LV10L-25

SymboltPDtEAtERtCFtCOtSFtStHtPtW

Parameter

Input or Feedback to Non-Registered OutputInput to Output EnableInput to Output DisableClock to FeedbackClock to OutputFeedback Setup TimeInput Setup TimeHold TimeClock PeriodClock Width

External Feedback 1/(tS + tCO)

FMAX

Internal Feedback 1/(tSF + tCF)No Feedback 1/(tP)

tAWtARtAP

Asynchronous Reset Width

Asynchronous Reset Recovery Time

Asynchronous Reset to Registered Output Reset

2525

151518

28

0012170126

32.247.683.3

Min

Typ151515510715

Max252525914

UnitsnsnsnsnsnsnsnsnsnsnsMHzMHzMHznsnsns

Input Test Waveforms and Measurement Levels

Output Test Loads:

Commercial

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Functional Logic Diagram AT22LV10(L)

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AT22LV10(L)

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AT22LV10(L)

Preload of Registered Outputs

The registers in the AT22LV10 and AT22LV10L are pro-vided with circuitry to allow loading of each register asyn-chronously with either a high or a low. This feature willsimplify testing since any state can be forced into the regis-ters to control test sequencing. A VIH level on the I/O pinwill force the register high; a VIL will force it low, indepen-dent of the polarity bit (C0) setting. The preload state isentered by placing an 11.5V to 13V signal on pin 8 on

DIPs, and pin 10 on SMPs. When the clock pin is pulsedhigh, the data on the I/O pins is placed into the ten regis-ters.

Level forced on registered output pin during preload cycle

VIHVIL

Register state after cycleHighLow

Power-Up ResetThe registers in the AT22LV10 and AT22LV10L aredesigned to reset during power up. At a point delayedslightly from VCC crossing 2.5V, all registers will be resetto the low state. The output state will depend on the polarityof the output buffer.

This feature is critical for state machine initialization. How-ever, due to the asynchronous nature of reset and theuncertainty of how VCC actually rises in the system, the fol-lowing conditions are required:

1.The VCC rise must be monotonis;

2.After reset occurs, all input and feedback setup

times must be met before driving the clock pin high, and

3.The clock must remain stable during tPR.

ParametertPR

DescriptionPower-Up Reset Time

MinTyp600

Max1000

Unitsns

Pin Capacitance

CINCOUTNote:

(f = 1 MHz, T = 25°C)(1)

Typ56

Max88

UnitspFpF

ConditionsVIN = 0VVOUT = 0V

1.Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

Erasure Characteristics

The entire fuse array of an AT22LV10 or AT22LV10L iserased after exposure to ultraviolet light at a wavelength of2537 Å. Complete erasure is assured after a minimum of20 minutes exposure using 12,000 µW/cm2 intensity lampsspaced one inch away from the chip. Minimum erase timefor lamps at other intensity ratings can be calculated from

the minimum integrated erasure dose of 15 W•sec/cm2. Toprevent unintentional erasure, an opaque label is recom-mended to cover the clear window on any UV erasablePLD which will be subjected to continuous fluorescentindoor lighting or sunlight.

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AT22LV10(L)

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AT22LV10(L)

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Ordering Information

tPD(ns)20

tS(ns)10

tCO(ns)14

Ordering CodeAT22LV10-20JCAT22LV10-20PCAT22LV10-20SCAT22LV10-20JIAT22LV10-20PIAT22LV10-20SI

25

12

17

AT22LV10-25JCAT22LV10-25PCAT22LV10-25SCAT22LV10-25JIAT22LV10-25PIAT22LV10-25SI

25

17

14

AT22LV10L-25JCAT22LV10L-25PCAT22LV10L-25SCAT22LV10L-25JIAT22LV10L-25PIAT22LV10L-25SI

Package28J24P324S28J24P324S28J24P324S28J24P324S28J24P324S28J24P324S

Operation RangeCommercial(0°C to 70°C)Industrial(-40°C to 85°C)Commercial(0°C to 70°C)Industrial(-40°C to 85°C)Commercial(0°C to 70°C)Industrial(-40°C to 85°C)

Package Type

28J24P324S

28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)

24-Lead, 0.300\" Wide, Plastic Dual Inline Package OTP (PDIP)24-Lead, 0.300\" Wide, Plastic Gull Wing Small Outline OTP (SOIC)

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AT22LV10(L)

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AT22LV10(L)

Packaging Information

28J, 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-018 AB24P3, 24-Lead, 0.300” Wide. Plastic Dual Inline Package (PDIP)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-011 AB.045(1.14) X 45°PIN NO.1IDENTIFY.045(1.14) X 30° - 45°.012(.305).008(.203)1.27(32.3)1.25(31.7)PIN1.266(6.76).250(6.35).090(2.29)MAX.005(.127)MIN.032(.813).026(.660).456(11.6)SQ.450(11.4).495(12.6)SQ.485(12.3).300(7.62) REF SQ.430(10.9)SQ.390(9.91).021(.533).013(.330)1.100(27.94) REF.043(1.09).020(.508).120(3.05).090(2.29).180(4.57).165(4.19).050(1.27) TYP.200(5.06)MAXSEATINGPLANE.151(3.84).125(3.18).110(2.79).090(2.29).065(1.65).040(1.02).325(8.26).300(7.62).012(.305).008(.203)0REF15.070(1.78).020(.508).023(.584).014(.356).022(.559) X 45° MAX (3X).400(10.2) MAX24S, 24-Lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)Dimensions in Inches and (Millimeters).020(.508).013(.330).299(7.60).420(10.7).291(7.39).393(9.98)PIN 1 ID.050(1.27) BSC.616(15.6).598(15.2).105(2.67).092(2.34).012(.305).003(.076).013(.330).009(.229)0REF8.050(1.27).015(.381)11