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专利名称：Test structure for integrated circuits发明人：De Winter, Rudi,Betts, William, Robert申请号：EP10154913.7申请日：20100226公开号：EP2224474A3公开日：20130220
专利附图：
摘要：A test insert 100 for an integrated circuit according to the present inventioncomprises access contacts 101, 103 and 104 and an electrical path 110. Furthermore,there may be additional access contacts and a plurality of different electrical paths. Theelectrical path 110 is comprised of a plurality of tracks 111, each track provided at a
single layer of the integrated circuit and connected to the other tracks 111 byinterconnecting vias 102. The vias 102 provide interlayer contacts and thus allow thetracks 111 to be connected into a single electrical track 110. In one embodiment, anaccess contact 104 is connected to ground; another contact 101 is connected to areference voltage: and connected to various points in the electrical path 110 aretransistor-resistor pairs 123. 124, 125. The transistor-resistor pairs 123, 124, 125 are inconnected between earth and a third access contact 103. If the electrical path is intact atthe track 111 connected to a transistor-resistor pair 123, 124, 125, a current can flowbetween contact 103 and the respective earth of the transistor-resistor pair 123, 124, 125.By analysing the current drawn from contact 103 it can be deduced whether the path 110is operational as a whole and if not, how far along the path 110 a fault lies. This cantherefore isolate a particular interconnection between layers or a particular layer asbeing faulty.
申请人：Melexis Tessenderlo NV
地址：Transportstraat 1 3980 Tessenderlo BE
国籍：BE
代理机构：Wilson Gunn
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