CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series GateOctober 1987Revised April 2002
CD4071BC • CD4081BC
Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate
General Description
The CD4071BC and CD4081BC quad gates are monolithiccomplementary MOS (CMOS) integrated circuits con-structed with N- and P-channel enhancement mode tran-sistors. They have equal source and sink currentcapabilities and conform to standard B series output drive.The devices also have buffered outputs which improvetransfer characteristics by providing very high gain.All inputs protected against static discharge with diodes toVDD and VSS.
Features
sLow power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LSs5V–10V–15V parametric ratingssSymmetrical output characteristics
sMaximum input leakage 1 µA at 15V over full temperature range
Ordering Code:
Order NumberCD4071BCMCD4071BCNCD4081BCMCD4081BCN
Package Number
M14AN14AM14AN14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
CD4071B
CD4081B
Top ViewTop View
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CD4071BC • CD4081BCSchematic Diagrams
CD4071B
1
/4 of device shown
J = A + B
Logical “1” = HIGHLogical “0” = LOW
*All inputs protected by standard CMOS protection circuit.
CD4081B
1
/4 of device shown
J = A • B
Logical “1” = HIGHLogical “0” = LOW
All inputs protected by standard CMOS protection circuit.
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CD4071BC • CD4081BCAbsolute Maximum Ratings(Note 1)
(Note 2)
Voltage at Any PinPower Dissipation (PD)Dual-In-LineSmall OutlineVDD Range
Storage Temperature (TS)Lead Temperature (TL)(Soldering, 10 seconds)
260°C700 mW500 mW
Recommended OperatingConditions
Operating Range (VDD)
Operating Temperature Range (TA)CD4071BC, CD4081BC
3VDC to 15 VDC
−0.5V to VDD +0.5V
−55°C to +125°C
−0.5 VDC to +18 VDC
−65°C to +150°C
Note 1: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed. Except for “Operating Tempera-ture Range” they are not meant to imply that the devices should be oper-ated at these limits. The table of “Electrical Characteristics” providesconditions for actual device operation.
Note 2: All voltages measured with respect to VSS unless otherwise speci-fied.
DC Electrical Characteristics (Note 2)
CD4071BC/CD4081BC SymbolIDD
Parameter
Quiescent DeviceCurrent
VOL
LOW LevelOutput Voltage
VOH
HIGH LevelOutput Voltage
VIL
LOW LevelInput Voltage
VIH
HIGH LevelInput Voltage
IOL
LOW Level OutputCurrent(Note 3)
IOH
HIGH Level OutputCurrent(Note 3)
IIN
Input Current
VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V
VDD = 5V, VO = 0.5VVDD = 10V, VO = 1.0VVDD = 15V, VO = 1.5VVDD = 5V, VO = 4.5VVDD = 10V, VO = 9.0VVDD = 15V, VO = 13.5VVDD = 5V, VO = 0.4VVDD = 10V, VO = 0.5VVDD = 15V, VO = 1.5VVDD = 5V, VO = 4.6VVDD = 10V, VO = 9.5VVDD = 15V, VO = 13.5VVDD = 15V, VIN = 0VVDD = 15V, VIN = 15V
Note 3: IOH and IOL are tested one output at a time.
Conditions
−55°CMin
Max0.250.51.00.05
Min
+25°CTyp0.0040.0050.006000
4.959.9514.95
51015246
3.57.011.00.511.33.4−0.51−1.3−3.4
3692.258.8−0.88−2.25−8.8−10−510−5
−0.10.11.53.04.0Max0.250.51.00.050.050.05
+125°CMin
Max7.515300.050.050.05
4.959.9514.95
1.53.04.0
3.57.011.00.92.4−0.36−0.9−2.4
−1.01.0
Units
µA
|IO| < 1 µA
4.95
|IO| < 1 µA
9.9514.95
0.050.05
V
V
1.53.04.0
3.57.011.00.1..2−0.−1.6−4.2
−0.10.1
V
V
0.880.36
mA
mA
µA
AC Electrical Characteristics (Note 4)
CD4071BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 kΩ, Typical temperature coefficient is 0.3%/°C
SymboltPHL
Parameter
Propagation Delay Time,HIGH-to-LOW Level
tPLH
Propagation Delay Time,LOW-to-HIGH Level
tTHL, tTLH
Transition Time
VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V
CINCPD
Average Input CapacitancePower Dissipation Capacity
Any InputAny Gate
Conditions
Typ1004030904030905040518
Max2501007025010070200100807.5
pFpFnsnsnsUnits
Note 4: AC Parameters are guaranteed by DC correlated testing.
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CD4071BC • CD4081BCAC Electrical Characteristics (Note 5)
CD4081BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 kΩ, Typical temperature coefficient is 0.3%/°C
SymboltPHL
Parameter
Propagation Delay Time,HIGH-to-LOW Level
tPLH
Propagation Delay Time,LOW-to-HIGH Level
tTHL, tTLH
Transition Time
VDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15VVDD = 5VVDD = 10VVDD = 15V
CINCPD
Average Input CapacitancePower Dissipation Capacity
Any InputAny Gate
Conditions
Typ10040301205035905040518
Max2501007025010070200100807.5
pFpFnsnsnsUnits
Note 5: AC Parameters are guaranteed by DC correlated testing.
Typical Performance Characteristics
Typical Transfer Characteristics
Typical Transfer Characteristics
Typical Transfer CharacteristicsTypical Transfer Characteristics
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CD4071BC • CD4081BCTypical Performance Characteristics (Continued)
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CD4071BC • CD4081BCPhysical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow
Package Number M14A
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CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series GatePhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.
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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
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