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专利名称：Method and apparatus for performing error
detection and correction with memorydevices
发明人：Sompong P. Olarig申请号：US08/940054申请日：19970930公开号：US05922080A公开日：19990713
摘要：A memory system for performing error detection and correction including amemory device that stores a plurality of data words, where each data word has a pluralityof data bits and at least one associated check bit. The memory system further includesmemory control circuitry that reads a plurality of data words in multiple cycles to form ablock word that includes a sufficient number of check bits to perform detection ofdouble bit errors and correction of single bit errors. A 72- bit block word is formed bygrouping smaller data words retrieved from the memory device. For a 9-bit device witheight data bits and one check bit, eight burst cycles may be used to retrieve a 72-bit datablock. Similarly, for 18-bit devices, four burst cycles may be used to retrieve the datablock and for 36-bit devices, two burst cycles may be used to retrieve the data block. Thememory system further includes error logic that receives and performs error detectionand correction upon the block word. The error logic groups the check bits of the blockword together, generates a syndrome code using a parity matrix, and uses the syndromecode and a corresponding syndrome table to detect and correct any bit errors in thedata.
申请人：COMPAQ COMPUTER CORPORATION, INC.
代理机构：Akin, Gump, Strauss, Hauer & Feld, LLP
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