KSZ95M资料

来源：微智科技网

元器件交易网www.cecb2b.comKS95MMicrelKS95MIntegrated 5-Port 10/100 Managed SwitchRev 1.12General Description

The KS95M is a highly integrated Layer-2 managed switch

with optimized BOM (Bill of Materials) cost for low port count,cost-sensitive 10/100Mbps switch systems. It also providesan extensive feature set such as tag/port-based VLAN, QoS(Quality of Service) priority, management, MIB counters, dualMII interfaces and CPU control/data interfaces to effectivelyaddress both current and emerging Fast Ethernet applica-tions.

The KS95M contains five 10/100 transceivers with pat-ented mixed-signal low-power technology, five MAC (MediaAccess Control) units, a high-speed non-blocking switchfabric, a dedicated address look-up engine, and an on-chipframe buffer memory.

All PHY units support 10BaseT and 100BaseTX. In addition,two of the PHY units support 100BaseFX (Ports 4 and 5).All support documentation can be found on Micrel’s web siteat www.micrel.com.

Features

•Integrated switch with five MACs and five Fast Ethernettransceivers fully compliant to IEEE 802.3u standard•Shared memory based switch fabric with fully non-blocking configuration

•1.4Gbps high-performance memory bandwidth

•10BaseT, 100BaseTX and 100BaseFX modes (FX inPorts 4 and 5)

•Dual MII configuration: MII-Switch (MAC or PHY modeMII) and MII-P5 (PHY mode MII)

•IEEE 802.1q tag-based VLAN (16 VLANs, full-rangeVID) for DMZ port, WAN/LAN separation or inter-VLANswitch links

•VLAN ID tag/untag options, per-port basis

•Programmable rate limiting 0Mbps to 100Mbps, ingressand egress port, rate options for high and low priority,per-port-basis

•Flow control or drop packet rate limiting (ingress port)•Integrated MIB counters for fully compliant statisticsgathering, 34 MIB counters per port

Functional Diagram

AutoMDI/MDIXAutoMDI/MDIXAutoMDI/MDIXAutoMDI/MDIXAutoMDI/MDIXMII-P5MDC, MDI/OMII-SW or SNIControl Reg I/FLED0[5:1]LED1[5:1]LED2[5:1]10/100T/Tx 110/100T/Tx 210/100T/Tx 310/100T/Tx/Fx 410/100T/Tx/Fx 510/100MAC 110/100MAC 210/100MAC 310/100MAC 410/100MAC 5SNISPIFIFO, Flow Control, VLAN Tagging, Priority1K look-upEngineQueueMgmntBufferMgmntFrameBuffersMIBCountersEEPROMI/FLED I/FControlRegistersKS95MMicrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com

December 20031M9999-120403

元器件交易网www.cecb2b.comKS95MFeatures (continued)

•Enable/Disable option for huge frame size up to 1916

bytes per frame

•IGMP v1/v2 snooping for multicast packet filtering•Special tagging mode to send CPU info on ingresspacket’s port value

•SPI slave (complete) and MDIO (MII PHY only) serialmanagement interface for control of register configura-tion

•MAC-id based security lock option

•Control registers configurable on-the-fly (port-priority,802.1p/d/q, AN...)

•CPU read access to MAC forwarding table entries•802.1d Spanning Tree Protocol

•Port mirroring/monitoring/sniffing:ingress and/or egresstraffic to any port or MII

•Broadcast storm protection with percent control–globaland per-port basis

•Optimization for fiber-to-copper media conversion•Full-chip hardware power-down support (registerconfiguration not saved)

•Per-port based software power-save on PHY (idle linkdetection, register configuration preserved)

•QoS/CoS packets prioritization supports: per port,802.1p and DiffServ based

•802.1p/q tag insertion or removal on a per port basis(egress)

•MDC and MDI/O interface support to access the MIIPHY control registers (not all control registers)•MII local loopback support

•On-chip Kbyte memory for frame buffering (notshared with 1K unicast address table)•Wire-speed reception and transmission

•Integrated look-up engine with dedicated 1K MACaddresses

•Full duplex IEEE 802.3x and half-duplex back pressureflow control

•Comprehensive LED support

•7-wire SNI support for legacy MAC interface

•Automatic MDI/MDI-X crossover for plug-and-play•Disable Automatic MDI/MDI-X option•Low power:

Core:1.8V

I/O:2.5V or 3.3V

•0.18µm CMOS technology

•Commercial temperature range:0°C to +70°C•Industrial temperature range:–40°C to +85°C•Available in 128-pin PQFP package

MicrelApplications

•••••••••

Broadband gateway/firewall/VPN

Integrated DSL or cable modem multi-port routerWireless LAN access point plus gatewayHome networking expansionStandalone 10/100 switchHotel/campus/MxU gatewayEnterprise VoIP gateway/phoneFTTx customer premise equipmentManaged media converter

Ordering Information

Part NumberKS95MKSZ95MKS95MI

Temperature Range

0°C to +70°C0°C to +70°C–40°C to +85°C

Package128-Pin PQFP

128-Pin PQFP Lead Free128-Pin PQFP

M9999-1204032December 2003

元器件交易网www.cecb2b.comKS95MRevision History

Revision1.001.011.021.031.04

Date11/05/0111/09/0112/03/0112/12/0112/13/01

Summary of ChangesCreated

Pinout Mux1/2, DVCC-IO 2.5/3.3V, feature list, register spec 11-09

MicrelEditorial changes, added new register and MIB descriptions. Added paragraph describing TOS registers.

Imported functional descriptions. Formatting.

Incorporate changes per engineering feedback as well as updating functional descriptions and addingnew timing information.

Changed Rev. and For. Modes to PHY and MAC modes respectively. Added MIIM clarification in “MIIManagement Interface” section. Reformatted section sequence. Added hex register addresses. Addedadvertisement ability descriptions.Inserted switch forwarding flow charts.

Added new KS95M block diagram, editorial changes, register descriptions changes and cross-references from functional descriptions to register and strap in options.

Changed FXSD pins to inputs, added new descriptions to “Configuration Interfaces” section.Edited pin descriptions.

Editorial changes in “Dynamic MAC Address table and “MIB Counters.” Updated figure 2 flowchart.Updated table 2 for MAC mode connections. Separate static MAC bit assignments for read and write.Edited read and write examples to MAC tables and MIB counters. Changed Table 3 KS95M signals to“S” suffix. Changed aging description in Register 2, bit 0. Changed “Port Registers” section and listed allport register addresses. Changed port control 11 description for bits [7:5]. Changed MIB counterdescriptions.

Changed MII setting in “Pin Descriptions.” Changed pu/pd descriptions for SMRXD2. “Register 18,”changed pu/pd description for forced flow control. “Illegal Frames. ” Edited large packet sizes back in.“Elecrical Characteristics,” Added in typical supply current numbers for 100 BaseTX and 10 BaseTX

operation. “Register 18,” Added in note for illegal half-duplex, force flow control. “Pin Description,” Addedextra X1 clock input description. “Elecrical Characteristics,” Updated to chip only current numbers.Added SPI Timing. Feature Highlights.

“Pin Description,” changed SMRXC and SMTXC to I/O. Input in MAC mode, output in PHY mode MII.“Elecrical Characteristics,” modified current consumption to chip only numbers. “Half-Duplex BackPressure,” added description for no dropped packets in half-duplex mode. Added recommendedoperating conditions. Added Idle mode current consumption in “Elecrical Characteristics,” added“Selection of Isolation Transformers,” Added 3.01kΩ resistor instructions for ISET “Pin Description”

section. Changed Polarity of transmit pairs in “Pin Description.” Changed description for Register 2, bit 1,in “Register Description” section. Added “Reset Timing” section.

“Register 3” changed 802.1x to 802.3x. “Register 6,” changed default column to disable flow control forpull-down, and enable flow control for pull-up. “Register 29” and “Register 0” indicate loop back is at thePHY. Added description to register 4 bit 2 to indicate that STPID packets from CPU to normal ports arenot allowed as 1522 byte tag packets. Fixed dynamic MAC address example errors in “Dynamic MACAddress Table.” Changed definition of forced MDI, MDIX in section “Register 29,” “Register 30” and“Register 0.” Added “Part Ordering Information.” Added Ambient operating temperature for KS95MIChanged pin 120 description to NC. Changed SPIQ pin description to Otri. Changed logo. Changedcontact information.

1.051.061.071.08

12/18/0112/20/011/22/013/1/02

1.095/17/02

1.107/29/02

1.1112/17/02

1.123/10/03

December 20033M9999-120403

元器件交易网www.cecb2b.comKS95MTable of Contents

MicrelSystem Level Applications.........................................................................................................................................7

Pin Description (by Number)......................................................................................................................................9Pin Description (by Name)........................................................................................................................................15Pin Configuration......................................................................................................................................................21Introduction...........................................................................................................................................................22Functional Overview:Physical Layer Transceiver................................................................................................22

100BaseTX Transmit...........................................................................................................................................22100BaseTX Receive............................................................................................................................................22PLL Clock Synthesizer.........................................................................................................................................22Scrambler/De-scrambler (100BaseTX only)........................................................................................................22100BaseFX Operation.........................................................................................................................................22100BaseFX Signal Detection...............................................................................................................................22100BaseFX Far End Fault...................................................................................................................................2310BaseT Transmit...............................................................................................................................................2310BaseT Receive................................................................................................................................................23Power Management.............................................................................................................................................23MDI/MDI-X Auto Crossover.................................................................................................................................23Auto-Negotiation..................................................................................................................................................23Functional Overview:Switch Core..........................................................................................................................24

Address Look-Up.................................................................................................................................................24Learning...........................................................................................................................................................24Migration...........................................................................................................................................................24Aging...........................................................................................................................................................24Forwarding...........................................................................................................................................................24Switching Engine.................................................................................................................................................24MAC Operation....................................................................................................................................................24

Inter-Packet Gap (IPG)................................................................................................................................24Backoff Algorithm.........................................................................................................................................24Late Collision...............................................................................................................................................26Illegal Frames..............................................................................................................................................26Flow Control.................................................................................................................................................26Half-Duplex Back Pressure..........................................................................................................................26Broadcast Storm Protection.........................................................................................................................26MII Interface Operation........................................................................................................................................26SNI Interface Operation.......................................................................................................................................28Advanced Functionality............................................................................................................................................28

Spanning Tree Support........................................................................................................................................28Special Tagging Mode.........................................................................................................................................29IGMP Support......................................................................................................................................................30Port Mirroring Support.........................................................................................................................................31VLAN Support......................................................................................................................................................31Rate Limit Support...............................................................................................................................................32Configuration Interface........................................................................................................................................33

I2C Master Serial Bus Configuration............................................................................................................35SPI Slave Serial Bus Configuration.............................................................................................................35MII Management Interface (MIIM).......................................................................................................................38

M9999-1204034December 2003

元器件交易网www.cecb2b.comKS95MRegister Description.................................................................................................................................................

Global Registers..................................................................................................................................................

Register 0 (0x00): Chip ID0.........................................................................................................................Register 1 (0x01): Chip ID1/Start Switch.....................................................................................................Register 2 (0x02): Global Control 0.............................................................................................................Register 3 (0x03): Global Control 1.............................................................................................................Register 4 (0x04): Global Control 2.............................................................................................................Register 5 (0x05): Global Control 3.............................................................................................................Register 6 (0x06): Global Control 4.............................................................................................................Register 7 (0x07): Global Control 5.............................................................................................................Register 8 (0x08): Global Control 6.............................................................................................................Register 9 (0x09): Global Control 7.............................................................................................................Register 10 (0x0A): Global Control 8...........................................................................................................Register 11 (0x0B): Global Control 9...........................................................................................................Port Registers......................................................................................................................................................

Register 16 (0x10):Port 1 Control 0...........................................................................................................Register 17 (0x11):Port 1 Control 1...........................................................................................................Register 18 (0x12):Port 1 Control 2...........................................................................................................Register 19 (0x13):Port 1 Control 3...........................................................................................................Register 20 (0x14):Port 1 Control 4...........................................................................................................Register 21 (0x15):Port 1 Control 5...........................................................................................................Register 22 (0x16):Port 1 Control 6...........................................................................................................Register 23 (0x17):Port 1 Control 7...........................................................................................................Register 24 (0x18):Port 1 Control 8...........................................................................................................Register 25 (0x19):Port 1 Control 9...........................................................................................................Register 26 (0x1A):Port 1 Control 10.........................................................................................................Register 27 (0x1B):Port 1 Control 11.........................................................................................................Register 28 (0x1C):Port 1 Control 12.........................................................................................................Register 29 (0x1D):Port 1 Control 13.........................................................................................................Register 30 (0x1E):Port 1 Status 0............................................................................................................Register 31 (0x1F):Port 1 Status 1.............................................................................................................Advanced Control Registers................................................................................................................................

Register 96 (0x60):TOS Priority Control Register 0...................................................................................Register 97 (0x61):TOS Priority Control Register 1...................................................................................Register 98 (0x62):TOS Priority Control Register 2...................................................................................Register 99 (0x63):TOS Priority Control Register 3...................................................................................Register 100 (0x):TOS Priority Control Register 4.................................................................................Register 101 (0x65):TOS Priority Control Register 5.................................................................................Register 102 (0x66):TOS Priority Control Register 6.................................................................................Register 103 (0x67):TOS Priority Control Register 7.................................................................................Register 104 (0x68):MAC Address Register 0...........................................................................................Register 105 (0x69):MAC Address Register 1...........................................................................................Register 106 (0x6A):MAC Address Register 2...........................................................................................Register 107 (0x6B):MAC Address Register 3...........................................................................................Register 108 (0x6C):MAC Address Register 4..........................................................................................Register 109 (0X6D):MAC Address Register 5..........................................................................................Register 110 (0x6E):Indirect Access Control 0..........................................................................................Register 111 (0x6F):Indirect Access Control 1..........................................................................................December 2003

Micrel39393939404041424243434343434444444547474747484949505050505050505050505050505050505151

M9999-120403

元器件交易网www.cecb2b.comKS95MMicrelRegister 112 (0x70):Indirect Data Register 8.............................................................................................51

Register 113 (0x71):Indirect Data Register 7.............................................................................................51Register 114 (0x72):Indirect Data Register 6.............................................................................................51Register 115 (0x73):Indirect Data Register 5.............................................................................................51Register 116 (0x74):Indirect Data Register 4.............................................................................................51Register 117 (0x75):Indirect Data Register 3.............................................................................................51Register 118 (0x76):Indirect Data Register 2.............................................................................................51Register 119 (0x77):Indirect Data Register 1.............................................................................................51Register 120 (0x78):Indirect Data Register 0.............................................................................................51Register 121 (0x79):Digital Testing Status 0..............................................................................................51Register 122 (0x7A):Digital Testing Status 1.............................................................................................51Register 123 (0x7B):Digital Testing Control 0............................................................................................51Register 124 (0x7C):Digital Testing Control 1............................................................................................51Register 125 (0x7D):Analog Testing Control 0..........................................................................................51Register 126 (0x7E):Analog Testing Control 1..........................................................................................52Register 127 (0x7F):Analog Testing Status...............................................................................................52

Static MAC Address..................................................................................................................................................53VLAN Address...........................................................................................................................................................55Dynamic MAC Address.............................................................................................................................................56MIB Counters...........................................................................................................................................................57MIIM Registers...........................................................................................................................................................60

Register 0: MII Control................................................................................................................................60Register 1: MII Status.................................................................................................................................61Register 2: PHYID HIGH.............................................................................................................................61Register 3: PHYID LOW.............................................................................................................................61Register 4: Advertisement Ability................................................................................................................61Register 5: Link Partner Ability....................................................................................................................62

Absolute Maximum Ratings.....................................................................................................................................63Operating Ratings.....................................................................................................................................................63Electrical Characteristics..........................................................................................................................................63Timing Diagrams.......................................................................................................................................................65Selection of Isolation Transformers........................................................................................................................72Qualified Magnetic Lists...........................................................................................................................................72Package Information.................................................................................................................................................73

M9999-1204036December 2003

元器件交易网www.cecb2b.comKS95MSystem Level Applications

10/100MAC 1Switch ControllerOn-Chip Frame BuffersMicrel10/100PHY 110/100PHY 210/100PHY 310/100PHY 410/100PHY 51-portWAN I/F4-portLAN10/100MAC 210/100MAC 310/100MAC 410/100MAC 5SPI/GPIOSPIEthernetMACCPUEthernetMACMII-SWMII-P5External WAN port PHY not neededFigure 1.Broadband Gateway

10/100MAC 1Switch ControllerOn-Chip Frame Buffers10/100PHY 110/100PHY 210/100PHY 310/100PHY 410/100PHY 54-portLAN10/100MAC 210/100MAC 310/100MAC 410/100MAC 5WAN PHY & AFE(xDSL, CM...)CPUSPI/GPIOSPIMII-SWMII-P5EthernetMACFigure 2.Integrated Broadband Router

December 20037M9999-120403

元器件交易网www.cecb2b.comKS95MMicrel10/100MAC 1Switch ControllerOn-Chip Frame Buffers10/100PHY 110/100PHY 210/100PHY 310/100PHY 410/100PHY 55-portLAN10/100MAC 210/100MAC 310/100MAC 410/100MAC 5Figure 3.Standalone Switch

M9999-1204038December 2003

元器件交易网www.cecb2b.comKS95MPin Description (by Number)

Pin Number

123456710111213141516171819202122232425262728293031

Pin NameTEST1GNDAVDDARRXP1RXM1GNDATXM1TXP1VDDATRXP2RXM2GNDATXM2TXP2VDDARGNDAISETVDDATRXP3RXM3GNDATXM3TXP3VDDATRXP4RXM4GNDATXM4TXP4GNDAVDDAR

PIIGndOOPIIGndOOGndP

44443333

Type(1)NCGndPIIGndOOPIIGndOOPGnd

22221111Port

Pin Function

NC for normal operation. Factory test pin.Analog ground1.8V analog VDD

Physical receive signal + (differential)Physical receive signal - (differential)Analog ground

Physical transmit signal - (differential)Physical transmit signal + (differential)2.5V analog VDD

Physical receive signal + (differential)Physical receive signal - (differential)Analog ground

Physical transmit signal - (differential)Physical transmit signal + (differential)1.8V analog VDDAnalog ground

Set physical transmit output current. Pull-down with a 3.01kΩ 1%

resistor.2.5V analog VDD

Physical receive signal + (differential)Physical receive signal - (differential)Analog ground

Physical transmit signal - (differential)Physical transmit signal + (differential)2.5V analog VDD

Physical receive signal + (differential)Physical receive signal - (differential)Analog ground

Physical transmit signal - (differential)Physical transmit signal + (differential)Analog ground1.8V analog VDD

MicrelNote:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

Ipd/O = Input w/ internal pull-down during reset, output pin otherwiseIpu/O = Input w/ internal pull-up during reset, output pin otherwisePU = Strap pin pull-upPD = Strap pin pull-downOtri = Output tristatedNC = No Connect

December 20039M9999-120403

元器件交易网www.cecb2b.comKS95MPin Number

323334353637383940414243444546

Pin NameRXP5RXM5GNDATXM5TXP5VDDATFXSD5FXSD4GNDAVDDARGNDAVDDARGNDAMUX1MUX2

Type(1)

IIGndOOPIIGndPGndPGndNCNC

5455Port55

Pin Function

Physical receive signal + (differential)Physical receive signal - (differential)Analog ground

Physical transmit signal - (differential)Physical transmit signal + (differential)2.5V analog VDD

Fiber signal detect/factory test pinFiber signal detect/factory test pinAnalog ground1.8V analog VDDAnalog ground1.8V analog VDDAnalog ground

MUX1 and MUX2 should be left unconnected for normal operation.

They are factory test pins.Mode

Normal Operation

Remote Analog Loopback Mode for Testing onlyReserved

Power Save Mode for Testing only

474849505152535455565758

Note:

1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

MicrelMux1NC011

Mux2NC101

PWRDN_NRESERVEGNDDVDDCPMTXENPMTXD3PMTXD2PMTXD1PMTXD0PMTXERPMTXCGNDD

IpuNCGndPIpdIpdIpdIpdIpdIpdOGnd

5555555

Full-chip power down. Active low.Reserved pin. No connect.Digital ground1.8V digital core VDDPHY[5] MII transmit enablePHY[5] MII transmit bit 3PHY[5] MII transmit bit 2PHY[5] MII transmit bit 1PHY[5] MII transmit bit 0PHY[5] MII transmit error

PHY[5] MII transmit clock. PHY mode MII.Digital ground

M9999-12040310December 2003

元器件交易网www.cecb2b.comKS95MPin Number

596061626365

Pin NameVDDIOPMRXCPMRXDVPMRXD3PMRXD2PMRXD1PMRXD0

Type(1)

POIpd/OIpd/OIpd/OIpd/OIpd/O

555555Port

Pin Function

3.3/2.5V digital VDD for digital I/O circuitryPHY[5] MII receive clock. PHY mode MIIPHY[5] MII receive data valid

PHY[5] MII receive bit 3. Strap option:PD (default) = enable flow

control; PU = disable flow control.

PHY[5] MII receive bit 2. Strap option:PD (default) = disable backpressure; PU = enable back pressure.

MicrelPHY[5] MII receive bit 1. Strap option:PD (default) = drop excessivecollision packets; PU = does not drop excessive collision packets.PHY[5] MII receive bit 0. Strap option: PD (default) = disable

aggressive back-off algorithm in half-duplex mode; PU = enable forperformance enhancement.

PHY[5] MII receive error. Strap option:PD (default) = 1522/1518 bytes;PU = packet size up to 1536 bytes.

PHY[5] MII carrier sense/Force duplex mode. See “Register 76” forport 4 only. PD (default) = Force half-duplex if auto-negotiation isdisabled or fails. PU = Force full-duplex if auto-negotiation is disabledor fails.

PHY[5] MII collision detect/ Force flow control. See “Register 66” forport 4 only. PD (default) = No force flow control. PU = Force flowcontrol.

Switch MII transmit enableSwitch MII transmit bit 3Switch MII transmit bit 2Switch MII transmit bit 1Switch MII transmit bit 0Switch MII transmit error

Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.Digital ground

3.3/2.5V digital VDD for digital I/O circuitry

Switch MII receive clock. Input in MAC mode, output in PHY mode MII.Switch MII receive data valid

Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MIIfull-duplex flow control; PU = Enable Switch MII full-duplex flow control.Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-duplex mode; PU = Switch MII in half-duplex mode.

6667

PMRXERPCRS

Ipd/OIpd/O

68PCOLIpd/O5

69707172737475767778798081

Note:

1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = Ground

SMTXENSMTXD3SMTXD2SMTXD1SMTXD0SMTXERSMTXCGNDDVDDIOSMRXCSMRXDVSMRXD3SMRXD2

IpdIpdIpdIpdIpdIpdI/OGndPI/OIpd/OIpd/OIpd/O

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

December 200311M9999-120403

元器件交易网www.cecb2b.comKS95MPin Number

8283

Pin NameSMRXD1SMRXD0

Type(1)Ipd/OIpd/O

Port

Pin Function

Switch MII receive bit 1. Strap option: PD (default) = Switch MII in

100Mbps mode; PU = Switch MII in 10Mbps mode.Switch MII receive bit 0; Strap option: LED Mode

PD (default) = Mode 0; PU = Mode 1. See “Register 11.”Mode 0

LEDX_2LEDX_1LEDX_0

848586

SCOLSCRSSCONF1

Ipd/OIpd/OIpd

Switch MII collision detectSwitch MII carrier senseDual MII configuration pinPin# (91, 86, 87):000001010011100101110111

878091929394959697

SCONF0GNDDVDDCLED5-2LED5-1LED5-0LED4-2LED4-1LED4-0LED3-2LED3-1

IpdGndPIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/O

55544433

Switch MIIDisable, OtriPHY Mode MIIMAC Mode MIIPHY Mode SNIDisablePHY Mode MIIMAC Mode MIIPHY Mode SNI

PHY [5] MIIDisable, OtriDisable, OtriDisable, OtriDisable, OtriDisablePHY Mode MIIPHY Mode MIIPHY Mode MIILnk/ActFulld/ColSpeed

MicrelMode 1100Lnk/Act10Lnk/ActFulld

Dual MII configuration pinDigital ground1.8V digital core VDD

LED indicator 2. Strap option: Aging setup. See “Aging” sectionPU (default) = Aging Enable; PD = Aging disable.

LED indicator 1. Strap option: PU (default): enable PHY MII I/FPD:tristate all PHY MII output. See “pin# 86 SCONF1.”LED indicator 0LED indicator 2LED indicator 1LED indicator 0LED indicator 2LED indicator 1

Note:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

M9999-12040312December 2003

元器件交易网www.cecb2b.comKS95MPin Number

99100101102103104105106107108109110111112

Pin NameLED3-0GNDDVDDIOLED2-2LED2-1LED2-0LED1-2LED1-1LED1-0MDCMDIOSPIQSPIC/SCLSPID/SDASPIS_N

Type(1)Ipu/OGndPIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpuI/OOtriI/OI/OIpu

222111AllAllAllAllAllAllPort3

Pin FunctionLED indicator 0Digital ground

3.3/2.5V digital VDD for digital I/OLED indicator 2LED indicator 1LED indicator 0LED indicator 2LED indicator 1LED indicator 0

Switch or PHY[5] MII management data clock

Switch or PHY[5] MII management data I/O.

Features internal pull down to define pin state when not driven.

Micrel(1) SPI serial data output in SPI slave mode; (2) Not used in I2C mastermode. See “pin# 113.”(1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at81KHz in I2C master mode. See “pin# 113.”(1) Serial data input in SPI slave mode; (2) Serial data input/output inI2C master mode See “pin# 113.”Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_Nis high, the KS95M is deselected and SPIQ is held in high impedancestate, a high-to-low transition to initiate the SPI data transfer; (2) Notused in I2C master mode.

Serial bus configuration pin

If EEPROM is not present, the KS95M will start itself with chipdefault (00)...Pin Config.PS[1:0]=00PS[1:0]=01PS[1:0]=10PS[1:0]=11

Serial Bus ConfigurationI2C Master Mode for EEPROMReserved

SPI Slave Mode for CPU InterfaceFactory Test Mode (BIST)

113PS1Ipd

114115116117118

Note:

1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = Ground

PS0RST_NGNDDVDDCTESTEN

IpdIpuGndPIpd

Serial bus configuration pin. See “pin# 113.”Reset the KS95M. Active low.Digital ground1.8V digital core VDD

NC for normal operation. Factory test pin.

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

December 200313M9999-120403

元器件交易网www.cecb2b.comKS95MPin Number

119120121122123124125126127128

Note:

1.P = Power supplyI = InputO = OutputI/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

MicrelPort

Pin Function

NC for normal operation. Factory test pin.No Connect

25MHz crystal clock connection/or 3.3V tolerant oscillator input.

Oscillator should be ±100ppm.25MHz crystal clock connection1.8V analog VDD for PLLAnalog ground1.8V analog VDDAnalog groundAnalog ground

NC for normal operation. Factory test pin.

Pin NameSCANENNCX1X2VDDAPGNDAVDDARGNDAGNDATEST2

Type(1)IpdNCIOPGndPGndGndNC

M9999-12040314December 2003

元器件交易网www.cecb2b.comKS95MPin Description (by Name)

Pin Number

393812442442163061221273440120127129881165876991710610510410310210198

Pin NameFXSD4FXSD5GNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDANCGNDAGNDAGNDDGNDDGNDDGNDDGNDDGNDDISETLED1-0LED1-1LED1-2LED2-0LED2-1LED2-2LED3-0

Ipu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/O

1112223

Type(1)

IIGndGndGndGndGndGndGndGndGndGndGndGndNCGndGndGndGndGndGndGndGnd

Port45

Pin Function

Fiber signal detect/factory test pin.Fiber signal detect/factory test pin.Analog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundAnalog groundNo connectAnalog groundAnalog groundDigital groundDigital groundDigital groundDigital groundDigital groundDigital ground

Set physical transmit output current. Pull-down with a 3.01kΩ 1%

resistor.LED indicator 0LED indicator 1LED indicator 2LED indicator 0LED indicator 1LED indicator 2LED indicator 0

MicrelNote:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

December 200315M9999-120403

元器件交易网www.cecb2b.comKS95MPin Number

979695949392919010710814546

Pin NameLED3-1LED3-2LED4-0LED4-1LED4-2LED5-0LED5-1LED5-2MDCMDIOTEST1MUX1MUX2

Type(1)Ipu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpu/OIpuI/ONCNCNC

Port33444555AllAll

Pin FunctionLED indicator 1LED indicator 2LED indicator 0LED indicator 1LED indicator 2LED indicator 0

LED indicator 1. Strap option:PU (default): enable PHY MII I/F.

PD:tristate all PHY MII output. See “pin# 86 SCONF1.”LED indicator 2. Strap option: Aging setup. See “Aging” section.(default) = Aging Enable;PD = Aging disableSwitch or PHY[5] MII management data clock.Switch or PHY[5] MII management data I/O.NC for normal operation. Factory test pin.

MUX1 and MUX2 should be left unconnected for normal operation.They are factory test pins.Mode

Normal Operation

Remote Analog Loopback Mode for Testing onlyReserved

Power Save Mode for Testing only

PCOL

Ipd/O

Mux1NC011

MicrelMux2NC101

PHY[5] MII collision detect/Force flow control. See “Register 18.”For port 4 only. PD (default) = No force flow control. PU = Force flowcontrol.

PHY[5] MII carrier sense/Force duplex mode See “Register 28.”For port 4 only. PD (default) = Force half-duplex if auto-negotiation isdisabled or fails. PU = Force full-duplex if auto-negotiation is disabledor fails.

PHY[5] MII receive clock. PHY mode MII.

PHY[5] MII receive bit 0. Strap option: PD (default) = disable

aggressive back-off algorithm in half-duplex mode; PU = enable forperformance enhancement.

PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessivecollision packets; PU = does not drop excessive collision packets.PHY[5] MII receive bit 2. Strap option: PD (default) = disable backpressure; PU = enable back pressure.

PHY[5] MII receive bit 3. Strap option: PD (default) = enable flowcontrol; PU = disable flow control.

67PCRSIpd/O5

6065

PMRXCPMRXD0

OIpd/O

6362

PMRXD1PMRXD2PMRXD3

Ipd/OIpd/OIpd/O

555

Note:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

M9999-12040316December 2003

元器件交易网www.cecb2b.comKS95MPin Number

616657555453525156114113

Pin NamePMRXDVPMRXERPMTXCPMTXD0PMTXD1PMTXD2PMTXD3PMTXENPMTXERPS0PS1

Type(1)Ipd/OIpd/OOIpdIpdIpdIpdIpdIpdIpdIpd

Port555555555

Pin Function

PHY[5] MII receive data valid.

MicrelPHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;

PU = packet size up to 1536 bytes.PHY[5] MII transmit clock. PHY mode MIIPHY[5] MII transmit bit 0PHY[5] MII transmit bit 1PHY[5] MII transmit bit 2PHY[5] MII transmit bit 3PHY[5] MII transmit enablePHY[5] MII transmit error

Serial bus configuration pin. See “pin# 113.”Serial bus configuration pin

If EEPROM is not present, the KS95M will start itself with chipdefault (00)...Pin Config.PS[1:0]=00PS[1:0]=01PS[1:0]=10PS[1:0]=11

Serial Bus ConfigurationI2C Master Mode for EEPROMReserved

SPI Slave Mode for CPU InterfaceFactory Test Mode (BIST)

474811551120263341019253211984

PWRDN_NRESERVERST_NRXM1RXM2RXM3RXM4RXM5RXP1RXP2RXP3RXP4RXP5SCANENSCOL

IpuNCIpuIIIIIIIIIIIpdIpd/O

1234512345

Full-chip power down. Active low.Reserved pin. No connect.Reset the KS95M. Active low.Physical receive signal - (differential)Physical receive signal - (differential)Physical receive signal - (differential)Physical receive signal - (differential)Physical receive signal - (differential)Physical receive signal + (differential)Physical receive signal + (differential)Physical receive signal + (differential)Physical receive signal + (differential)Physical receive signal + (differential)NC for normal operation. Factory test pin.Switch MII collision detect.

Note:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

December 200317M9999-120403

元器件交易网www.cecb2b.comKS95MPin Number

8786

Pin NameSCONF0SCONF1

Type(1)IpdIpd

Port

Pin Function

Dual MII configuration pinDual MII configuration pinPin# (91, 86, 87):000001010011100101110111

857883

SCRSSMRXCSMRXD0

Ipd/OI/OIpd/O

Switch MII carrier sense

Switch MIIDisable, OtriPHY Mode MIIMAC Mode MIIPHY Mode SNIDisablePHY Mode MIIMAC Mode MIIPHY Mode SNI

PHY [5] MIIDisable, OtriDisable, OtriDisable, OtriDisable, OtriDisablePHY Mode MIIPHY Mode MIIPHY Mode MII

MicrelSwitch MII receive clock. Input in MAC mode, output in PHY mode MII.Switch MII receive bit 0; Strap option: LED Mode

PD (default) = Mode 0; PU = Mode 1. See “Register 11.”Mode 0

LEDX_2LEDX_1LEDX_0

Lnk/ActFulld/ColSpeed

Mode 1100Lnk/Act10Lnk/ActFulld

8281807975737271706974

SMRXD1SMRXD2SMRXD3SMRXDVSMTXCSMTXD0SMTXD1SMTXD2SMTXD3SMTXENSMTXER

Ipd/OIpd/OIpd/OIpd/OI/OIpdIpdIpdIpdIpdIpd

Switch MII receive bit 1. Strap option:PD (default) = Switch MII in100Mbps mode; PU = Switch MII in 10Mbps mode.

Switch MII receive bit 2. Strap option:PD (default) = Switch MII infull-duplex mode; PU = Switch MII in half-duplex mode.

Switch MII receive bit 3. Strap option:PD (default) = Disable SwitchMII full-duplex flow control; PU = Enable Switch MII full-duplex flow control.Switch MII receive data valid

Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.Switch MII transmit bit 0Switch MII transmit bit 1Switch MII transmit bit 2Switch MII transmit bit 3Switch MII transmit enableSwitch MII transmit error

Note:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

M9999-12040318December 2003

元器件交易网www.cecb2b.comKS95MPin Number

110111109112

Pin NameSPIC/SCLSPID/SDASPIQSPIS_N

Type(1)I/OI/OOtriIpu

PortAllAllAllAll

Pin Function

Micrel(1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at 81KHz

in I2C master mode. See “pin# 113.”(1) Serial data input in SPI slave mode; (2) Serial data input/output inI2C master mode. See “pin# 113.”(1) SPI serial data output in SPI slave mode; (2) Not used in I2C mastermode. See “pin# 113.”Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_Nis high, the KS95M is deselected and SPIQ is held in high impedancestate, a high-to-low transition to initiate the SPI data transfer; (2) Notused in I2C master mode.

No connect for normal operation. Factory test pin.No Connect for normal operation. Factory test pin.

1281188142329367132228351234143315311251243750

TEST2TESTENTXP1TXP2TXP3TXP4TXP5TXM1TXM2TXM3TXM4TXM5VDDAPVDDARVDDARVDDARVDDARVDDARVDDARVDDATVDDATVDDATVDDATVDDC

NCIpdOOOOOOOOOOPPPPPPPPPPPP

1234512345

Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal + (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)Physical transmit signal - (differential)1.8V analog VDD for PLL1.8V analog VDD1.8V analog VDD1.8V analog VDD1.8V analog VDD1.8V analog VDD1.8V analog VDD2.5V analog VDD2.5V analog VDD2.5V analog VDD2.5V analog VDD1.8V digital core VDD

Note:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

December 200319M9999-120403

元器件交易网www.cecb2b.comKS95MPin Number

1175977100121122

Pin NameVDDCVDDCVDDIOVDDIOVDDIOX1X2

Type(1)

PPPPPIO

Port

Pin Function1.8V digital core VDD1.8V digital core VDD

3.3/2.5V digital VDD for digital I/O circuitry3.3/2.5V digital VDD for digital I/O circuitry3.3/2.5V digital VDD for digital I/O circuitry

25MHz crystal clock connection/or 3.3V tolerant oscillator input.

Oscillator should be ±100ppm.25MHz crystal clock connection.

MicrelNote:

1.P = Power supplyI = InputO = Output

I/O = Bi-directionalGnd = Ground

Ipu = Input w/ internal pull-upIpd = Input w/ internal pull-down

M9999-12040320December 2003

元器件交易网www.cecb2b.comKS95MDecember 2003

LED2-0LED1-2LED1-1LED1-0MDCMDIOSPIQSPIC/SCLSPID/SDASPIS_NPS1PS0RST_NGNDDVDDCTESTENSCANENNCX1X2VDDAPGNDAVDDARGNDAGNDATEST21031Pin Configuration

128-Pin PQFP (PQ)

3965TEST1GNDAVDDARRXP1RXM1GNDATXM1TXP1VDDATRXP2RXM2GNDATXM2TXP2VDDARGNDAISETVDDATRXP3RXM3GNDATXM3TXP3VDDATRXP4RXM4GNDATXM4TXP4GNDAVDDARRXP5RXM5GNDATXM5TXP5VDDATFXSD5LED2-1LED2-2VDDIOGNDDLED3-0LED3-1LED3-2LED4-0LED4-1LED4-2LED5-0LED5-1LED5-2VDDCGNDDSCONF0SCONF1SCRSSCOLSMRXD0SMRXD1SMRXD2SMRXD3SMRXDVSMRXCVDDIOGNDDSMTXCSMTXERSMTXD0SMTXD1SMTXD2SMTXD3SMTEXNPCOLPCRSPMRXERPMRXD0PMRXD1PMRXD2PMRXD3PMRXDVPMRXCVDDIOGNDDPMTXCPMTXERPMTXD0PMTXD1PMTXD2PMTXD3PMTXENVDDCGNDDRESERVEPWRDN_NMUX2MUX1GNDAVDDARGNDAVDDARGNDAFXSD4M9999-120403

Micrel元器件交易网www.cecb2b.comKS95MIntroduction

MicrelThe KS95M contains five 10/100 physical layer transceivers and five MAC (Media Access Control) units with an integrated

layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is asa five-port switch with the fifth port decoupled from the physical port. In this mode access to the fifth MAC is provided throughan MII (Media Independent Interface). This is useful for implementing an integrated broadband router. The third mode usesthe dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where thefifth PHY may be accessed through the MII-P5 port.

The KS95M has the flexibility to reside in a managed or unmanaged design. In a managed design, a host processor hascomplete control of the KS95M via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design isachieved through I/O strapping or EEPROM programming at system reset time.

On the media side, the KS95M supports IEEE 802.3 10BaseT, 100BaseTX on all ports, and 100BaseFX on ports 4 and 5.The KS95M can be used as two separate media converters.

Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the designmore efficient and allows for lower power consumption and smaller chip die size.

The major enhancements from the KS95E to the KS95M are support for host processor management, a dual MII interface,tag as well as port based VLAN, spanning tree protocol support, IGMP snooping support, port mirroring support and rate limitingfunctionality.

Functional Overview:Physical Layer Transceiver

100BaseTX Transmit

The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion,MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from theMAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler.The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The outputcurrent is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complieswith the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BaseT outputis also incorporated into the 100BaseTX transmitter.

100BaseTX Receive

The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clockrecovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel conversion. The receiving sidestarts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since theamplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics tooptimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons ofincoming signal strength against some known cable characteristics, it then tunes itself for optimization. This is an ongoingprocess and can self-adjust against environmental changes such as temperature variations.

The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used tocompensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit convertsthe MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used toconvert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder.Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.

PLL Clock Synthesizer

The KS95M generates 125MHz, 42MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated froman external 25MHz crystal or oscillator.

Scrambler/De-scrambler (100BaseTX only)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. Thedata is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.

100BaseFX Operation

100BaseFX operation is very similar to 100BaseTX operation except that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is nostandard that supports fiber auto-negotiation.

100BaseFX Signal Detection

The physical port runs in 100BaseFX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V.The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.25V reference, indicating signal

M9999-120403

22December 2003

元器件交易网www.cecb2b.comKS95MMicreldetect, and FXSDx ‘L’ is below the 1.25V reference to indicate no signal. When FXSDx is below 0.6V then 100BaseFX mode

is disabled. Since there is no auto-negotiation for 100BaseFX mode, ports 4 and 5 must be forced to either full or half-duplex.Note that strap in options exist to set duplex mode for port 4, but not for port 5.

100BaseFX Far End Fault

Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, thetransmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. Thefar end fault may be disabled through register settings.

10BaseT Transmit

The output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetics. They areinternally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least27dB below the fundamental when driven by an all-ones Manchester-encoded signal.

10BaseT Receive

On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and aPLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. Asquelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP orRXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signaland the KS95M decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.

Power Management

The KS95M features a per port power down mode. To save power the user can power down ports that are not in use by settingport control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entirechip will be shut down.

MDI/MDI-X Auto Crossover

The KS95M supports MDI/MDI-X auto crossover. This facilitates the use of either a straight connection CAT-5 cable or acrossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmitand receive pairs from the Micrel device. This can be highly useful when end users are unaware of cable types and can alsosave on an additional uplink configuration connection. The auto crossover feature may be disabled through the port controlregisters.

Auto-Negotiation

The KS95M conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows UTP(Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto-negotiation the link partnersadvertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS95M isforced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel modebecause while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixedsignal protocol.

The flow for the link set up is depicted in Figure 4.

Start Auto NegotiationForce Link SettingNoParallelOperationYesBypassAuto-Negotiationand Set Link ModeAttemptAuto-NegotiationListen for 100BaseTXIdlesListen for 10BaseTLink PulsesNoJoin FlowLink Mode Set ?YesLink Mode SetFigure 4.Auto-Negotiation

December 2003

M9999-120403

元器件交易网www.cecb2b.comKS95MFunctional Overview:Switch Core

Address Look-Up

MicrelThe internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus

switching information. The KS95M is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-uptables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addressesit can learn.

Learning

The internal look-up engine will update its table with a new entry if the following conditions are met:

•The received packet’s SA (Source Address) does not exist in the look-up table.

•The received packet is good; the packet has no receiving errors, and is of legal length.

The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, thelast entry of the table will be deleted first to make room for the new entry.

Migration

The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly.Migration happens when the following conditions are met:

•The received packet’s SA is in the table but the associated source port information is different.•The received packet is good; the packet has no receiving errors, and is of legal length.

The look-up engine will update the existing record in the table with the new source port information.

Aging

The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stampis used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record fromthe table. The look-up engine constantly performs the aging process and will continuously remove aging records. The agingperiod is 300 + 75 seconds. This feature can be enabled or disabled through Register 3 or by external pull-up or pull-downresistors on LED[5][2]. See “Register 3” section.

Forwarding

The KS95M will forward packets using an algorithm that is depicted in the following flowcharts. Figure 5 shows stage oneof the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destinationaddress, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping,port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2) as shown in Figure 6. This is where thepacket will be sent.

The KS95M will not forward the following packets:

•Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.•802.3x pause frames. The KS95M will intercept these packets and perform the appropriate actions.

•“Local” packets. Based on DA (Destination Address) look-up. If the destination port from the look-up table matchesthe port where the packet was from, the packet is defined as “local.”

Switching Engine

The KS95M features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operatesin store and forward mode, while the efficient switching mechanism reduces overall latency.

The KS95M has a kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode canbe programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool.In the second mode, each port is only allowed to use 1/5 of the total buffer pool. There are a total of 512 buffers available. Eachbuffer is sized at 128B.

MAC (Media Access Controller) Operation

The KS95M strictly abides by IEEE 802.3 standards to maximize compatibility.Inter-Packet Gap (IPG)If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the currentpacket is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.Backoff AlgorithmThe KS95M implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” backoff. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in register 3. See “Register3.”M9999-120403

24December 2003

元器件交易网www.cecb2b.comKS95MMicrelStartPTF1=NULLNOVLAN IDVALID?-Search VLAN table-Ingress VLAN filtering-Discard NPVID checkYESSearch complete.Get PTF1 fromstatic tableFOUNDSearch StaticTableThis search is based onDA or DA+FIDNOTFOUNDSearch complete.Get PTF1 fromdynamic tableFOUNDDynamicTableSearchThis search is based onDA+FIDNOTFOUNDSearch complete.Get PTF1 fromVLAN tablePTF1Figure 5.DA Look-Up Flowchart–Stage 1

PTF1Spanning TreeProcess-Check receiving port’s receive enable bit-Check destination port’s transmit enable bit-Check whether packets are special (BPDUor specified)IGMP Process-Applied to MAC #1 to #4-MAC#5 is reserved for microprocessor-IGMP will be forwarded to port 5Port MirrorProcess-RX Mirror-TX Mirror-RX or TX Mirror-RX and TX MirrorPort VLANMembershipCheckPTF2Figure 6.DA Resolution Flowchart–Stage 2

December 2003

M9999-120403

元器件交易网www.cecb2b.comKS95MMicrelLate CollisionIf a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.Illegal FramesThe KS95M discards frames less than bytes and can be programmed to accept frames up to 1536 bytes in register 4.For special applications, the KS95M can also be programmed to accept frames up to 1916 bytes in register 4. Since theKS95M supports VLAN tags, the maximum sizing is adjusted when these tags are present.Flow ControlThe KS95M supports standard 802.3x flow control frames on both transmit and receive sides.

On the receive side, if the KS95M receives a pause control frame, the KS95M will not transmit the next normal frame untilthe timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires,the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flowcontrol packets from the KS95M will be transmitted.

On the transmit side, the KS95M has intelligent and efficient ways to determine when to invoke flow control. The flow controlis based on availability of the system resources, including available buffers, available transmit queues and available receivequeues.

The KS95M will flow control a port, which just received a packet, if the destination port resource is being used up. TheKS95M will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Oncethe resource is freed up, the KS95M will send out the other flow control frame (XON) with zero pause time to turn off theflow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from beingactivated and deactivated too many times.

The KS95M will flow control all ports if the receive queue becomes full.Half-Duplex Back PressureA half-duplex back pressure option (note: not in 802.3 standards) is also provided. The activation and deactivation conditionsare the same as the above in full-duplex mode. If back pressure is required, the KS95M will send preambles to defer theother stations’ transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard,after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carriersense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the porthas packets to send during a back pressure situation, the carrier-sense-type back pressure will be interrupted and thosepackets will be transmitted instead. If there are no more packets to send, carrier-sense-type back pressure will be active againuntil switch resources are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense isgenerated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets.To ensure no packet loss in 10BaseT or 100BaseTX half-duplex modes, the user must enable the following:

•Aggressive backoff (register 3, bit 0)

•No excessive collision drop (register 4, bit 3)•Back pressure (register 4, bit 5)

These bits are not set as the default because this is not the IEEE standard.Broadcast Storm ProtectionThe KS95M has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcastpackets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and availablespace in transmit queues). The KS95M has the option to include “multicast packets” for storm control. The broadcast stormrate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 50msinterval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the ratelimit mechanism starts to count the number of bytes during the interval. The rate definition is described in Register 6 andRegister 7. The default setting for registers 6 and 7 is 0x4A, which is 74 decimal. This is equal to a rate of 1%, calculated asfollows:

148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4A

MII Interface Operation

The MII (Media Independent Interface) is specified by the IEEE 802.3 committee and provides a common interface betweenphysical layer and MAC layer devices. The KS95M provides two such interfaces. The MII-P5 interface is used to connectto the fifth PHY, whereas the MII-SW interface is used to connect to the fifth MAC. Each of these MII interfaces contains twodistinct groups of signals, one for transmission and the other for receiving. Table 5 describes the signals used in the MII-P5interface.

M9999-12040326December 2003

元器件交易网www.cecb2b.comKS95MMII signalMTXENMTXERMTXD3MTXD2MTXD1MTXD0MTXCMCOLMCRSMRXDVMRXERMRXD3MRXD2MRXD1MRXD0MRXCMDCMDIO

DescriptionTransmit enableTransmit errorTransmit data bit 3Transmit data bit 2Transmit data bit 1Transmit data bit 0Transmit clockCollision detectionCarrier senseReceive data validReceive errorReceive data bit 3Receive data bit 2Receive data bit 1Receive data bit 0Receive clock

Management data clockManagement data I/O

KS95M signalPMTXENPMTXERPMTXD[3]PMTXD[2]PMTXD[1]PMTXD[0]PMTXCPCOLPCRSPMRXDVPMRXERPMRXD[3]PMRXD[2]PMRXD[1]PMRXD[0]PMRXCMDCMDIO

MicrelTable 1.MII–P5 Signals (PHY Mode)

PHY Mode ConnectionExternal

MACMTXENMTXERMTXD3MTXD2MTXD1MTXD0MTXCMCOLMCRSMRXDVMRXERMRXD3MRXD2MRXD1MRXD0MRXC

KS95MSignalSMTXENSMTXERSMTXD[3]SMTXD[2]SMTXD[1]SMTXD[0]SMTXCSCOLSCRSSMRXDVNot usedSMRXD[3]SMRXD[2]SMRXD[1]SMRXD[0]SMRXC

MAC Mode ConnectionExternalPHYMTXENMTXERMTXD3MTXD2MTXD1MTXD0MTXCMCOLMCRSMRXDVMRXERMRXD3MRXD2MRXD1MRXD0MRXC

KS95MSignalSMRXDVNot usedSMRXD[3]SMRXD[2]SMRXD[1]SMRXD[0]SMRXCSCOLSCRSSMTXENSMTXERSMTXD[3]SMTXD[2]SMTXD[1]SMTXD[0]SMTXC

Table 2.MII–SW Signals

December 200327M9999-120403

元器件交易网www.cecb2b.comKS95MMicrelThe MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These

interfaces are nibble wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on thetransmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicatorsthat convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicatesa collision has occurred during transmission.

Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is notprovided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from thephysical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for thisconfiguration. For PHY mode operation, if the device interfacing with the KS95M has an MRXER pin, it should be tied low.For MAC mode operation, if the device interfacing with the KS95M has an MTXER pin, it should be tied low.

SNI Interface Operation

The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. Thisinterface can be directly connected to these types of devices. The signals are divided into two groups, one for transmissionand the other for reception. The signals involved are described in Table 3.

SNI SignalTXENTXDTXCCOLCRSRXDRXC

DescriptionTransmit enableSerial transmit dataTransmit clockCollision detectionCarrier senseSerial receive dataReceive clock

KS95M SignalSMTXENSMTXD[0]SMTXCSCOLSMRXDVSMRXD[0]SMRXC

Table 3.SNI Signals

This interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on thetransmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid.For half-duplex operation there is a signal that indicates a collision has occurred during transmission.

Advanced Functionality

Spanning Tree Support

To support spanning tree, port 5 is the designated port for the processor.

The other ports (port 1 - port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive enable”and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3 and 4, respectively. The followingdescription shows the port setting and software actions taken for each of the five spanning tree states.Disable state:the port should not forward or receive any packets. Learning is disabled.Port setting:“transmit enable = 0, receive enable = 0, learning disable = 1”

Software action:the processor should not send any packets to the port. The switch may still send specific packets to theprocessor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard thosepackets. Note:processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.Blocking state:only packets to the processor are forwarded. Learning is disabled.Port setting:“transmit enable = 0, receive enable = 0, learning disable = 1”

Software action:the processor should not send any packets to the port(s) in this state. The processor should program the statictable with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should also be set so that the switchwill forward those specific packets to the processor. Address learning is disabled on the port in this state.Listening state:only packets to and from the processor are forwarded. Learning is disabled.Port setting:“transmit enable = 0, receive enable = 0, learning disable = 1”

Software action:The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDUpackets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processormay send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is disabled onthe port in this state.

M9999-12040328December 2003

元器件交易网www.cecb2b.comKS95MMicrelLearning state:only packets to and from the processor are forwarded. Learning is enabled.Port setting:“transmit enable = 0, receive enable = 0, learning disable = 0”

Forwarding state:packets are forwarded and received normally. Learning is enabled.Port setting:“transmit enable = 1, receive enable = 1, learning disable = 0”

Special Tagging Mode

The special tagging mode is designed for spanning tree protocol IGMP snooping and is flexible for use in other applications.The special tagging mode, similar to 802.1q, requires software to change network drivers to insert/modify/strip/interpret thespecial tag. This mode is enabled by setting both register 11 bit 0 and register 80-bit 2.

802.1q Tag Format

TPID (tag protocol identifier, 0x8100) + TCI

Special Tag Format

STPID (special tag identifier, 0x8100)+TCI 0x810+4 bit for “port mask”)+ TCI

Table 4.Special Tagging Mode Format

The STPID will only be seen and used on the port 5 interface, which should be connected to a processor. Packets from theprocessor to the switch should be tagged with STPID and the port mask defined as below:

“0001” packet to port 1 only“0010” packet to port 2 only“0100” packet to port 3 only“1000” packet to port 4 only

“0011” packet broadcast to port 1 and port 2......

“1111” packet broadcast to port 1, 2, 3 and 4.

“0000” normal tag, will use KS95M internal look-up result. Normal packets should use this setting. If packets from theprocessors do not have a tag, the KS95M will treat them as normal packets and an internal look-up will be performed.The KS95M uses a non-zero “port mask” to bypass the look-up result and override any port setting, regardless of port states(blocking, disable, listening, learning). The Table 5 shows the egress rules when dealing with STPID.

December 200329M9999-120403

元器件交易网www.cecb2b.comKS95MIngress Tag Field(0x810+ port mask)

Tx Port

“Tag Insertion”

Tx Port“Tag Removal”

Egress Action to Tag Field••••

MicrelModify tag field to 0x8100Recalculate CRC

No change to TCI if not null VID

Replace VID with ingress (port 5) port VID if null VID

(0x810+ port mask)01

•(STPID + TCI) will be removed•Padding to bytes if necessary•Recalculate CRC••••••••

Modify tag field to 0x8100Recalculate CRC

No change to TCI if not null VID

Replace VID with ingress (port 5) port VID if null VIDModify tag field to 0x8100Recalculate CRC

No change to TCI if not null VID

Replace VID with ingress (port 5) port VID if null VID

(0x810+ port mask)10

(0x810+ port mask)11

Not TaggedDon’t careDon’t careDetermined by the dynamic MAC address table

Table 5.STPID Egress Rules (Processor to Switch Port 5)

For packets from regular ports (port 1 - port 4) to port 5, the port mask is used to tell the processor which port the packet wasreceived on, defined as:

“0001” from port 1,“0010” from port 2,“0100” from port 3,“1000” from port 4

No values other than the previous four defined should be received in this direction in the special mode. Table 6 shows theegress rule for this direction.

Ingress Packets

Tagged with 0x8100 + TCI

Egress Action to Tag Field••••

Modify TPID to 0x810 + “port mask,” which indicates source portNo change to TCI, if VID is not nullReplace null VID with ingress port VIDRecalculate CRC

Not tagged

•Insert TPID to 0x810 + “port mask,” which indicates source port•Insert TCI with ingress port VID•Recalculate CRC

Table 6.STPID Egress Rules (Switch to Processor)

IGMP Support

There are two parts involved to support IGMP in layer 2. The first part is “IGMP” snooping. The switch will trap IGMP packetsand forward them only to the processor port. The IGMP packets are identified as IP packets (either Ethernet IP packets or IEEE802.3 SNAP IP packets) AND IP version = 0x4 AND protocol number = 0x2. The second part is “multicast address insertion”in the static MAC table. Once the multicast address is programmed in the static MAC table, the multicast session will be trimmedto the subscribed ports, instead of broadcasting to all ports. To enable this feature, set register 5 bit 6 to 1. Also “special tagmode” needs to be enabled, so that the processor knows which port the IGMP packet was received on. Enable “special tagmode” by setting both register 11 bit 0 and register 80-bit 2.

M9999-12040330December 2003

元器件交易网www.cecb2b.comKS95MPort Mirroring Support

MicrelKS95M supports “port mirror” comprehensively as:

1.“Receive Only” mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example,port 1 is programmed to be “rx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, received on port1, is destined to port 4 after the internal look-up. The KS95M will forward the packet to both port 4 and port 5.KS95M can optionally forward even “bad” received packets to port 5.

2.“Transmit Only” mirror on a port. All the packets transmitted on the port will be mirrored on the sniffer port. Forexample, port 1 is programmed to be “tx sniff,” and port 5 is programmed to be the “sniffer port.” A packet, receivedon any of the ports, is destined to port 1 after the internal look-up. The KS95M will forward the packet to both port1 and port 5.

3.“Receive and Transmit” mirror on two ports. All the packets received on port A AND transmitted on port B will bemirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit 0 to 1. For example, port 1 is programmedto be “rx sniff,” port 2 is programmed to be “transmit sniff” and port 5 is programmed to be the “sniffer port.” A packet,received on port 1, is destined to port 4 after the internal look-up. The KS95M will forward the packet to port 4 only,since it does not meet the “AND” condition. A packet, received on port 1, is destined to port 2 after the internal look-up. The KS95M will forward the packet to both port 2 and port 5.

Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.” All theseper port features can be selected through Register 17.

VLAN Support

KS95M supports 16 active VLANs out of 4096 possible VLANs specified in IEEE 802.1q. KS95M provides a 16-entryVLAN table, which converts VID (12 bits) to FID (4bits) for address look-up. If a non-tagged or null-VID-tagged packet isreceived, the ingress port VID is used for look-up. In the VLAN mode, the look-up process starts with VLAN table look-up todetermine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned. Ifthe VID is valid, FID is retrieved for further look-up. FID+DA is used to determine the destination port. FID+SA is used forlearning purposes.

DA found inStatic MAC table

NoNoYesYesYesYes

DA+FID found inDynamic MAC table

NoYesDon’t care

USE FID Flag?Don’t careDon’t care

0111

FID Match?Don’t careDon’t careDon’t care

NoNoYes

Action

Broadcast to the membership ports defined in theVLAN table bit[20:16]

Send to the destination port defined in thedynamic MAC table bit[54:52]

Send to the destination port(s) defined in thestatic MAC table bit[52:48]

Broadcast to the membership ports defined inthe VLAN table bit[20:16]

Send to the destination port defined in thedynamic MAC table bit[54:52]

Send to the destination port(s) defined in thestatic MAC table bit[52:48]

Table 7.FID+DA Look-Up in the VLAN Mode

December 200331M9999-120403

元器件交易网www.cecb2b.comKS95MSA+FID found in

Dynamic MAC tableNoYes

Action

The SA+FID will be learned into the dynamic table.Time stamp will be updated

MicrelTable 8.FID+SA Look-Up in the VLAN Mode

Advanced VLAN features are also supported in KS95M, such as “VLAN ingress filtering” and “discard non PVID” definedin register 18 bit 6 and bit 5. These features can be controlled on a port basis.

Rate Limit Support

KS95M supports hardware rate limiting on “receive” and “transmit” independently on a per port basis. It also supports ratelimiting in a priority or non-priority environment. The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps.The KS95M uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the ratelimit mechanism starts to count the number of bytes during this interval.

For receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the“one second” interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmedgreater than or equal to 128Kbps and the byte counter is 8K bytes below the limit, the flow control will be triggered. If the ratelimit is programmed lower than 128Kbps and the byte counter is 2K bytes below the limit, the flow control will be triggered.For transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port untilthe “one second” interval expires.

If priority is enabled, the KS95M can support different rate controls for both high priority and low priority packets. This canbe programmed through registers 21–27.

M9999-12040332December 2003

元器件交易网www.cecb2b.comKS95MConfiguration Interface

MicrelThe KS95M can function as a managed switch or unmanaged switch. If no EEPROM or micro-controller exists, the

KS95M will operate from its default setting. Some default settings are configured via strap in options as indicated in the tablebelow.

Pin #14546

Pin NameTEST1MUX1MUX2

PU/PDNCNCNC

Description

NC for normal operation. Factory test pin.

MUX1 and MUX2 should be left unconnected for normal operation.They are factory test pinsMode

Normal Operation

Remote Analog Loopback Mode for Testing onlyReserved

Power Save Mode for Testing only

6263656667

PMRXD3PMRXD2PMRXD1PMRXD0PMRXERPCRS

Ipd/OIpd/OIpd/OIpd/OIpd/OIpd/O

Mux1NC011

Mux2NC101

PHY[5] MII receive bit 3. Strap option:PD (default) = enable flow control;PU = disable flow control.

PHY[5] MII receive bit 2. Strap option:PD (default) = disable back pressure;PU = enable back pressure.

PHY[5] MII receive bit 1. Strap option:PD (default) = drop excessive collisionpackets; PU = does not drop excessive collision packets.

PHY[5] MII receive bit 0. Strap option:PD (default) = disable aggressive back-offalgorithm in half-duplex mode; PU = enable for performance enhancement.PHY[5] MII receive error. Strap option:PD (default) = 1522/1518 bytes;PU = packet size up to 1536 bytes.

PHY[5] MII carrier sense/Force duplex mode. See “Register 76” for port 4 only.PD (default) = Force half-duplex if auto-negotiation is disabled or fails. PU = Forcefull-duplex if auto-negotiation is disabled or fails.

PHY[5] MII collision detect/ Force flow control. See “Register 66” for port 4 only.PD (default) = No force flow control. PU = Force flow control.

Switch MII receive bit 3. Strap option:PD (default) = Disable Switch MII full-duplexflow control; PU = Enable Switch MII full-duplex flow control.

Switch MII receive bit 2. Strap option:PD (default) = Switch MII in full-duplex mode;PU = Switch MII in half-duplex mode.

Switch MII receive bit 1. Strap option:PD (default) = Switch MII in 100Mbps mode;PU = Switch MII in 10Mbps mode.

Switch MII receive bit 0; Strap option: LED Mode PD (default) = Mode 0;PU = Mode 1. See “Register 11.”Mode 0

LEDX_2LEDX_1LEDX_0

Lnk/ActFulld/ColSpeed

Mode 1100Lnk/Act10Lnk/ActFulld

6880818283

PCOLSMRXD3SMRXD2SMRXD1SMRXD0

Ipd/OIpd/OIpd/OIpd/OIpd/O

December 200333M9999-120403

元器件交易网www.cecb2b.comKS95MPin #86

Pin NameSCONF1

PU/PDIpd

Description

Dual MII configuration pin.Pin# (91, 86, 87):000001010011100101110111

879091113

SCONF0LED5-2LED5-1PS1

IpdIpu/OIpu/OIpd

Switch MIIDisable, OtriPHY Mode MIIMAC Mode MIIPHY Mode SNIDisablePHY Mode MIIMAC Mode MIIPHY Mode SNI

PHY [5] MIIDisable, OtriDisable, OtriDisable, OtriDisable, OtriDisablePHY Mode MIIPHY Mode MIIPHY Mode MII

MicrelDual MII configuration pin.

LED indicator 2. Strap option: Aging setup. See “Aging” section.

PU (default) = Aging Enable; PD = Aging disable.

LED indicator 1. Strap option:PU (default): enable PHY MII I/F. PD:tristate all PHYMII output. See “pin# 86 SCONF1.”

Serial bus configuration pin

If EEPROM is not present, the KS95M will start itself with chipdefault (00)...Pin ConfigurationPS[1:0]=00PS[1:0]=01PS[1:0]=10PS[1:0]=11

Serial Bus ConfigurationI2C Master Mode for EEPROMReserved

SPI Slave Mode for CPU InterfaceFactory Test Mode (BIST)

114128

PS0TEST2

IpdNC

Serial bus configuration pin. See “pin# 113.”NC for normal operation. Factory test pin.

M9999-12040334December 2003

元器件交易网www.cecb2b.comKS95MMicrelI2C Master Serial Bus ConfigurationIf a 2-wire EEPROM exists, the KS95M can perform more advanced features like “broadcast storm protection,” “rate control,”etc. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the “Memory Map,”except the status registers. After reset, the KS95M will start to read all 110 registers sequentially from the EEPROM. Theconfiguration access time (tprgm) is less than 15ms as shown in Figure 7.

RST_NSCLSDA............tprgm<15 msFigure 7.KS95M EEPROMConfiguration Timing Diagram

To configure the KS95M with a pre-configured EEPROM use the following steps:

1. At the board level, connect pin 110 on the KS95M to the SCL pin on the EEPROM. Connect pin 111 on theKS95M to the SDA pin on the EEPROM.

2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00”. This puts the KS95M serial bus configurationinto I2C master mode.

3. Be sure the board level reset signal is connected to the KS95M reset signal on pin 115 (RST_N).

4. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note thatthe first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all other datawill be ignored.

5. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on theKS95M. After the reset is deasserted, the KS95M will begin reading configuration data from the EEPROM. Theconfiguration access time (tprgm) is less than 15ms.

Note: For proper operation, make sure pin 47 (PWRDN_N) is not asserted during the reset operation.

SPI Slave Serial Bus ConfigurationThe KS95M can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including “VLAN,”“IGMP snooping,” “MIB counters,” etc. The external master device can access any register from register 0 to register 127randomly. The system should configure all the desired settings before enabling the switch in the KS95M. To enable theswitch, write a one to register 1 bit 0.

Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speedconfiguration time, the KS95M also supports multiple reads or writes. After a byte is written to or read from the KS95M,the internal address counter automatically increments if the SPI Slave Select signal (SPIS_N) continues to be driven low. IfSPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on SPIQ. If SPIS_N is keptlow after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to the next address. AssertingSPIS_N high terminates a read or write operation. This means that the SPIS_N signal must be asserted high and then low againbefore issuing another command and address. The address counter wraps back to zero once it reaches the highest address.Therefore the entire register set can be written to or read from by issuing a single command and address.

The KS95M is able to support a 5MHz SPI bus. A high performance SPI master is recommended to prevent internal counteroverflow.

December 200335M9999-120403

元器件交易网www.cecb2b.comKS95MTo use the KS95M SPI:

1. At the board level, connect KS95M pins as follows:

KS95MPin Number112110111109

KS95MSignal NameSPIS_NSPICSPIDSPIQ

Microprocessor SignalDescriptionSPI Slave SelectSPI Clock

Master Out Slave InputMaster In Slave Output

MicrelTable 9.SPI Connections

2. Set the input signals PS[1:0] (pins 113 and 114 respectively) to “10” to set the serial configuration to SPI slave mode.3. Power up the board and assert a reset signal. After reset, the start switch bit in register 1 will be set to ‘0’. Configurethe desired settings in the KS95M before setting the start register to ‘1’.

4. Write configuration to registers using a typical SPI write data cycle as shown in Figure 8 or SPI multiple write as shownin Figure 10. Note that data input on SPID is registered on the rising edge of SPIC.

5. Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure 9 ora multiple read as shown in Figure 11. Note that read data is registered out of SPIQ on the falling edge of SPIC.6. After configuration is written and verified, write a ‘1’ to register 1 bit 0 to begin KS95M operation.

M9999-12040336December 2003

元器件交易网www.cecb2b.comKS95MMicrelSPIS_NSPICSPIDSPIQX00000010A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0WRITE COMMANDWRITE ADDRESSWRITE DATAFigure 8.SPI Write Data Cycle

SPIS_NSPICSPIDSPIQX00000011A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0READ COMMANDREAD ADDRESSREAD DATAFigure 9.SPI Read Data Cycle

December 200337M9999-120403

元器件交易网www.cecb2b.comKS95MMicrelSPIS_NSPICSPIDSPIQX00000010A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0WRITE COMMANDSPIS_NSPICSPIDSPIQD7D6D5D4D4D2D1D0D7D6D5WRITE ADDRESSByte 1D4D3D2D1D0D7D6D5D4D3D2D1D0Byte 2Byte 3 ...Byte NFigure 10.SPI Multiple Write

SPIS_NSPICSPIDSPIQX00000011A7A6A5A4A3A2A1A0XD7XD6XD5XD4XD3XD2XD1XD0READ COMMANDSPIS_NSPICSPIDSPIQXD7READ ADDRESSByte 1XD6XD5XD4XD3XD2XD1XD0XD7XD6XD5XD4XD3XD2XD1XD0XD7XD6XD5XD4XD3XD2XD1XD0Byte 2Byte 3Byte NFigure 11.SPI Multiple Read

MII Management Interface (MIIM)

A standard MIIM interface is provided for all five PHY devices in the KS95M. An external device with MDC/MDIO capability

is able to read PHY status or to configure PHY settings. For details on the MIIM interface standard please reference the IEEE802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in theKS95M. It can only access the standard MII registers. See “MIIM Registers.” The SPI interface, on the other hand, can beused to access the entire KS95M feature set.

M9999-12040338December 2003

元器件交易网www.cecb2b.comKS95MRegister Description

OffsetDecimal0-12-1112-1516-2930-3132-4546-4748-6162-63-7778-7980-9394-9596-103104-109110-111112-120121-122123-124125-126127

Hex0x00-0x010x02-0x0B0x0C-0x0F0x10-0x1D0x1E-0x2F0x20-0x2D0x2E-0x2F0x30-0x3D0x3E-0x3F0x40-0x4D0x4E-0x4F0x50-0x5D0x5E-0x5F0x60-0x670x68-0x6D0x6E-0x6F0x70-0x780x79-0x7A0x7B-0x7C0x7D-0x7E0x7F

DescriptionChip ID RegistersGlobal Control RegistersReserved

Port 1 Control RegistersPort 1 Status RegistersPort 2 Control RegistersPort 2 Status RegistersPort 3 Control RegistersPort 3 Status RegistersPort 4 Control RegistersPort 4 Status RegistersPort 5 Control RegistersPort 5 Status RegistersTOS Priority Control RegistersMAC Address Registers

Indirect Access Control RegistersIndirect Data RegistersDigital Testing Status RegistersDigital Testing Control RegistersAnalog Testing Control RegistersAnalog Testing Status Register

MicrelGlobal Registers

Address

Name

Description

Mode

Default

Family ID

Chip family

0x95

Chip IDRevision IDStart Switch

0x0 is assigned to M series. (95M)Revision ID

1, start the chip when external pins (PS1, PS0) = (1,0)

or (0,1). Note: in (PS1,PS0) = (0,0) mode, the chip willstart automatically, after trying to read the external

EEPROM. If EEPROM does not exist, the chip will usedefault values for all internal registers. If EEPROM ispresent, the contents in the EEPROM will be checked.The switch will check: (1) Register 0 = 0x95,

(2) Register 1 [7:4] = 0x0. If this check is OK, thecontents in the EEPROM will override chip registerdefault values.=0, chip will not start when external pins(PS1, PS0) = (1,0) or (0,1).

Note: (PS1, PS0) = (1,1) for factory test only.RORORW

0x00x20x0

December 200339M9999-120403

元器件交易网www.cecb2b.comKS95MAddress

Name

Description

Mode

Default

Reserved

802.1p base priority

Reserved

Used to classify priority for incoming 802.1q packets.

“User priority” is compared against this value.≥ : classified as high priority.< : classified as low priority.

1, enable PHY MII interface.

(Note: if not enabled, the switch will tri-state all outputs)

R/WR/W

0x00x4

Micrel3Enable PHY MIIR/W

Pin LED[5][1]strap option.Pull-down (0):isolate. Pull-up(1):Enable.Note:LED[5][1]has internalpull-up.0x1

2Buffer share mode

1, buffer pool is shared by all ports. A port can usemore buffer when other ports are not busy.

0, a port is only allowed to use 1/5 of the buffer pool.1 the switch will drop packets with 0x8808 in T/Lfiled, or DA=01-80-C2-00-00-01.

0, the switch will drop packets qualified as“flow control” packets.

1, link change from “link” to “no link” will cause fastaging (<800µs) to age address table faster. After anage cycle is complete, the age logic will return tonormal (300 + 75 seconds ). Note: If any port isunplugged, all addresses will be automatically agedout.

R/W

1UNH modeR/W0

0Link change ageR/W0

Pass all frames

1, switch all packets including bad ones. Used solelyfor debugging purpose. Works in conjunction withsniffer mode.Reserved

0, will enable transmit flow control based on AN result.1, will not enable transmit flow control regardless ofAN result.

R/W

Reserved

IEEE 802.3x Transmitflow control disable

R/WR/W

Pin PMRXD3strap option.Pull-down(0):Enable tx flow

control. Pull-up (1):Disable tx/rxflow control.Note:PMRXD3has internal pull-down.Pin PMRXD3 strapoption. Pull-down(0):Enable rx flowcontrol. Pull-up (1):Disable tx/rx flowcontrol.

Note:PMRXD3has internal pull-down.0

IEEE 802.3x Receiveflow control disable

0, will enable receive flow control based on AN result.1, will not enable receive flow control regardless ofAN result.

Note: Bit 5 and bit 4 default values are controlled bythe same pin, but they can be programmedindependently.

R/W

3Frame Length field check

1, will check frame length field in the IEEE packets.If the actual length does not match, the packet will bedropped. (for L/T < 1500)

R/W

M9999-12040340December 2003

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NameAging enable

Description

1, Enable age function in the chip

0, Disable aging function

ModeR/W

Default

MicrelPin LED[5][2] strapoption. Pull-down(0): Aging disable.Pull-up (1):Agingenable.

Note: LED[5][2]has internal pullup.0

Pin PMRXD0 strapoption. Pull-down(0):Disableaggressive backoff. Pull-up (1):Aggressive backoff.

Note: PMRXD0has internal pulldown.10

Fast age enableAggressive backoff enable

1, Turn on fast age (800µs)

1, Enable more aggressive backoff algorithm in halfduplex mode to enhance performance. This is not anIEEE standard.

R/WR/W

Unicast port-VLANmismatch discard

This feature is used for port-VLAN.(described in reg17, reg33...)

1, all packets can not cross VLAN boundary.0, unicast packets (excluding unknown/

mutlicast/broadcast) can cross VLAN boundary.1, “Broadcast Storm Protection” does not include

multicast packets. Only DA=FFFFFFFFFFFF packetswill be regulated.

0, “Broadcast Storm Protection” includes DA =FFFFFFFFFFFF and DA[40] = 1 packets.1, carrier sense based backpressure is selected.0, collision based backpressure is selected.

1, fair mode is selected. In this mode, if a flow controlport and a non-flow control port talk to the same

destination port, packets from the non-flow control portmay be dropped. This is to prevent the flow control portfrom being flow controlled for an extended period of time.0, in this mode, if a flow control port and a non-flowcontrol port talk to the same destination port, the flowcontrol port will be flow controlled. This may not be “fair”to the flow control port.

1, the switch will not drop packets when 16 or morecollisions occur.

0, the switch will drop packets when 16 or morecollisions occur.

R/W

Multicast Stormprotection disable

R/W1

Back pressure modeFlow control and backpressure fair mode

R/WR/W

3No excessive collision dropR/W

Pin PMRXD1 strapoption. Pull-down(0): Drop

excessive collisionpackets. Pull-up (1):Don’t drop

excessive collisionpackets.

Note:PMRXD1has internal pulldown.0

2Huge packet support

1, will accept packet sizes up to 1916 bytes (inclusive).This bit setting will override setting from bit 1 of thesame register.

0, the max packet size will be determined by bit 1 of thisregister.

R/W

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Name

Legal Maximum Packet

size check disable

Description

1, will accept packet sizes up to 1536 bytes (inclusive).0, 1522 bytes for tagged packets (not including packetswith STPID from CPU to ports 1-4), 1518 bytes for

untagged packets. Any packets larger than the specifiedvalue will be dropped.

ModeR/W

Default

MicrelPin PMRXERstrap option.Pull-down (0):1518/1522 bytepackets. Pull-up(1): 1536 bytepackets.

Note:PMRXERhas internal pulldown.0

0Priority Buffer reserve

1, Each output queue is pre-allocated 48 buffers,used exclusively for high priority packets. It isrecommended to enable this when priority queuefeature is turned on.

0, No reserved buffers for high priority packets.

R/W

802.1q VLAN enable

1, 802.1q VLAN mode is turned on. VLAN table needsto set up before the operation.0, 802.1q VLAN is disabled.

1, IGMP snoop enabled. All the IGMP packets will beforwarded to switch MII port.0, IGMP snoop disabled.

1, direct mode on port 5. This is a special mode for theswitch MII interface. Using preamble before MRXDV todirect switch to forward packets, bypassing internallook-up.

0, normal operation.

1, packets forwarded to switch MII interface will bepre-tagged with the source port number.(preamble before MRXDV)0, normal operation.

00 = always deliver high priority packets first.01 = deliver high/low packets at ratio 10/1.10 = deliver high/low packets at ratio 5/1.11 = deliver high/low packets at ratio 2/1.

1, the last 5 digits in the VID field are used as a maskto determine which port(s) the packet should beforwarded to.0, no tag masks.

1, will do Rx AND Tx sniff (both source port anddestination port need to match).

0, will do Rx OR Tx sniff (Either source port or

destination port needs to match). This is the modeused to implement Rx only sniff.

R/W

IGMP snoop enable onSwitch MII interfaceEnable direct mode onSwitch MII interface

R/W0

5R/W0

Enable pre tag onSwitch MII interface

R/W0

3-2Priority Scheme selectR/W00

1Enable “tag” maskR/W0

0Sniff mode selectR/W0

Switch MII backpressure enableSwitch MII halfduplex mode

1, enable half-duplex back pressure on switch MIIinterface.

0, disable back pressure on switch MII interface.1, enable MII interface half-duplex mode.0, enable MII interface full-duplex mode.

R/W

6R/W

Pin SMRXD2 strapoption. Pull-down(0): Full duplexmode. Pull-up(1):Half duplexmode Note:SMRXD2 hasinternal pull down.M9999-12040342December 2003

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NameSwitch MII flow

control enable

Description

1, enable full-duplex flow control on switch MII interface.0, disable full-duplex flow control on switch MII interface.

ModeR/W

Default

MicrelPin SMRXD3 strapoption. Pull-down(0):disable flowcontrol. Pull-up(1):enable flow control.Note: SMRXD3has internal pull-down.Pin SMRXD1 strapoption. Pull-down(0):Enable

100Mbps. Pull-up(1):Enable 10Mpbs.Note:SMRXD1has internal pull-down.0000

4Switch MII 10BT

1, the switch interface is in 10Mbps mode.0, the switch interface is in 100Mbps mode.

R/W

32-0

Null VID replacementBroadcast storm

protection rate Bit [10:8]

1, will replace null VID with port VID(12 bits).0, no replacement for null VID.

This along with the next register determines how many“ byte blocks” of packet data allowed on an input portin a preset period. The period is 50ms for 100BT or500ms for 10BT. The default is 1%.

R/WR/W

Broadcast storm

protection rate Bit [7:0]

This along with the previous register determines howmany “ byte blocks” of packet data are allowed on aninput port in a preset period. The period is 50ms for100BT or 500ms for 10BT. The default is 1%.

R/W

0x4A(1)

Note:

1.148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4A

Factory testing

Reserved

R/W

0x24

Factory testing

Reserved

R/W

0x28

Factory testing

Reserved

R/W

0x24

ReservedLED mode

N/A

0 = led mode 01 = led mode 1

R/W

Pin SMRXD0 strapoption. Pull-down(0):Enabled ledmode 0. Pull-up(1):Enabled led mode 1.Note:SMRXD0 hasinternal pull-down 0.Mode 0

LEDX_2LEDX_1LEDX_0

Special TPID mode

Lnk/ActFulld/ColSpeed

Mode 1100Lnk/Act10Lnk/ActFulld

R/W

Used for direct mode forwarding from port 5.See “Spanning Tree” functional description.

December 200343M9999-120403

元器件交易网www.cecb2b.comKS95MPort Registers

MicrelThe following registers are used to enable features that are assigned on a per port basis. The register bit assignments are

the same for all ports, but the address for each port is different, as indicated.

Register 16 (0x10): Port 1 Control 0Register 32 (0x20): Port 2 Control 0Register 48 (0x30): Port 3 Control 0Register (0x40): Port 4 Control 0Register 80 (0x50): Port 5 Control 0Address7

Name

Broadcast stormprotection enableDiffserv priority

classification enable802.1p priority

classification enablePort-based priorityclassification enable

Description

1, enable broadcast storm protection for ingress packetson the port.

0, disable broadcast storm protection.

1, enable DiffServ priority classification for ingresspackets on port.

0, disable DiffServ function.

1, enable 802.1p priority classification for ingresspackets on port.0, disable 802.1p.

1, ingress packets on the port will be classified as highpriority if “DiffServ” or “802.1p” classification is notenabled or fails to classify.

0, ingress packets on port will be classified as low priorityif “DiffServ” or “802.1p” classification is not enabled orfails to classify.

Note:“DiffServ”, “802.1p” and port priority can beenabled at the same time. The OR’ed result of 802.1pand DSCP overwrites the port priority.Reserved

1, when packets are output on the port, the switch willadd 802.1q tags to packets without 802.1q tags whenreceived. The switch will not add tags to packets alreadytagged. The tag inserted is the ingress port’s “port VID”0, disable tag insertion.

1, when packets are output on the port, the switch willremove 802.1q tags from packets with 802.1q tagswhen received. The switch will not modify packetsreceived without tags.0, disable tag removal.

1, the port output queue is split into high and lowpriority queues.

0, single output queue on the port. There is no prioritydifferentiation even though packets are classified intohigh or low priority.

ModeR/W

Default0

6R/W0

5R/W0

4R/W0

ReservedTag insertion

R/WR/W

1Tag removalR/W0

0Priority enableR/W0

Register 17 (0x11): Port 1 Control 1Register 33 (0x21): Port 2 Control 1Register 49 (0x31): Port 3 Control 1Register 65 (0x41): Port 4 Control 1Register 81 (0x51): Port 5 Control 1Address7

NameSniffer port

Description

1, Port is designated as sniffer port and will transmitpackets that are monitored.0, Port is a normal port.

1, All the packets received on the port will be markedas “monitored packets” and forwarded to the designated“sniffer port.”

0, no receive monitoring.

ModeR/W

Default0

6Receive sniffR/W0

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NameTransmit sniff

Description

1, All the packets transmitted on the port will be

marked as “monitored packets” and forwarded to thedesignated “sniffer port.”0, no transmit monitoring.

Define the port’s “Port VLAN membership.” Bit 4 standsfor port 5, bit 3 for port 4... bit 0 for port 1. The Port canonly communicate within the membership. A ‘1’

includes a port in the membership, a ‘0’ excludes a portfrom membership.

ModeR/W

Default0

Micrel4-0Port VLAN membershipR/W0x1f

Register 18 (0x12): Port 1 Control 2Register 34 (0x22): Port 2 Control 2Register 50 (0x32): Port 3 Control 2Register 66 (0x42): Port 4 Control 2Register 82 (0x52): Port 5 Control 2Address76

NameReserved

Ingress VLAN filtering

DescriptionReserved

1, the switch will discard packets whose VID port

membership in VLAN table bit[20:16] does not includethe ingress port.

0, no ingress VLAN filtering.

1, the switch will discard packets whose VID doesnot match ingress port default VID.0, no packets will be discarded.

1, will always enable rx and tx flow control on the port,regardless of AN result.

0, the flow control is enabled based on AN result.Note: Setting a port for both half-duplex and forcedflow control is an illegal configuration. For half-duplexenable back pressure.R/WMode

Default0x00

5Discard Non PVID packetsR/W0

4Force flow controlR/W

For port 4 only,there is a specialconfiguration pinto set the default,Pin PCOL strapoption. Pull-down(0):No Force flowcontrol Pull-up(1):Force flowcontrol.

Note: PCOL hasinternal pull down.Pin PMRXD2 strapoption. Pull-down(0):disable backpressure. Pull-up(1):enable backpressure.

Note: PMRXD2 hasinternal pull-down.110

3Back pressure enable

1, enable port’s half-duplex back pressure.0, disable port’s half-duplex back pressure.

R/W

210

Note:

Transmit enableReceive enableLearning disable

1, enable packet transmission on the port.0, disable packet transmission on the port.1, enable packet reception on the port.0, disable packet reception on the port.1, disable switch address learning capability.0, enable switch address learning.

R/WR/WR/W

Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section.

December 200345M9999-120403

元器件交易网www.cecb2b.comKS95MRegister 19 (0x13): Port 1 Control 3

Register 35 (0x23): Port 2 Control 3Register 51 (0x33): Port 3 Control 3Register 67 (0x43): Port 4 Control 3Register 83 (0x53): Port 5 Control 3Address7-0

Name

Default tag [15:8]

Description

Port’s default tag, containing7-5:user priority bits4: CFI bit

3-0 : VID[11:8]

ModeR/W

Default0

MicrelRegister 20 (0x14): Port 1 Control 4Register 36 (0x24): Port 2 Control 4Register 52 (0x34): Port 3 Control 4Register 68 (0x44): Port 4 Control 4Register 84 (0x54): Port 5 Control 4Address7-0

Name

Default tag [7:0]

Description

Default port 1’s tag, containing7-0: VID[7:0]

ModeR/W

Default1

Note:

Registers 19 and 20 (and those corresponding to other ports) serve two purposes:(1) Associated with the ingress untagged packets, and used foregress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look-up.

Register 21 (0x15): Port 1 Control 5Register 37 (0x25): Port 2 Control 5Register 53 (0x35): Port 3 Control 5Register 69 (0x45): Port 4 Control 5Register 85 (0x55): Port 5 Control 5Address7-0

Name

Transmit high priorityrate control [7:0]

Description

This along with port control 7, bits [3:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be transmitted. (In a unit of 4K bytes in aone second period.)

ModeR/W

Default0

Register 22 (0x16): Port 1 Control 6Register 38 (0x26): Port 2 Control 6Register 54 (0x36): Port 3 Control 6Register 70 (0x46): Port 4 Control 6Register 86 (0x56): Port 5 Control 6Address7-0

Name

Transmit low priorityrate control [7:0]

Description

This along with port control 7, bits [7:4] form a 12-bitfield to determine how many “32Kbps” low priorityblocks can be transmitted. (In a unit of 4K bytes in aone second period.)

ModeR/W

Default0

Register 23 (0x17): Port 1 Control 7Register 39 (0x27): Port 2 Control 7Register 55 (0x37): Port 3 Control 7Register 71 (0x47): Port 4 Control 7Register 87 (0x57): Port 5 Control 7Address7-4

Name

Transmit low priorityrate control [11:8]

Description

This along with port control 6, bits [7:0] form a 12-bitfield to determine how many “32Kbps” low priorityblocks can be transmitted. (In a unit of 4K bytes in aone second period.)

This along with port control 5, bits [7:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be transmitted. (In unit of 4K bytes in aone second period.)

ModeR/W

Default0

3-0

Transmit high priorityrate control [11:8]

R/W0

M9999-12040346December 2003

元器件交易网www.cecb2b.comKS95MRegister 24 (0x18): Port 1 Control 8

Register 40 (0x28): Port 2 Control 8Register 56 (0x38): Port 3 Control 8Register 72 (0x48): Port 4 Control 8Register 88 (0x58): Port 5 Control 8Address7-0

Name

Receive high priorityrate control [7:0]

Description

This along with port control 10, bits [3:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be received. (In a unit of 4K bytes in a onesecond period.)

ModeR/W

Default0

MicrelRegister 25 (0x19): Port 1 Control 9Register 41 (0x29): Port 2 Control 9Register 57 (0x39): Port 3 Control 9Register 73 (0x49): Port 4 Control 9Register (0x59): Port 5 Control 9Address7-0

Name

Receive low priorityrate control [7:0]

Description

This along with port control 10, bits [7:4] form a 12-bitfield to determine how many “32Kbps” low priorityblocks can be received. (In a unit of 4K bytes in a onesecond period.)

ModeR/W

Default0

Register 26 (0x1A): Port 1 Control 10Register 42 (0x2A): Port 2 Control 10Register 58 (0x3A): Port 3 Control 10Register 74 (0x4A): Port 4 Control 10Register 90 (0x5A): Port 5 Control 10Address7-4

Name

Receive low priorityrate control [11:8]

Description

This along with port control 9, bits [7:0] form a 12-bitfield to determine how many “32Kbps” low priority

blocks can be received. (In a unit of 4K bytes in a onesecond period.)

This along with port control 8, bits [7:0] form a 12-bitfield to determine how many “32Kbps” high priorityblocks can be received. (In a unit of 4K bytes in a onesecond period.)

ModeR/W

Default0

3-0

Receive high priorityrate control [11:8]

R/W0

Register 27 (0x1B): Port 1 Control 11Register 43 (0x2B): Port 2 Control 11Register 59 (0x3B): Port 3 Control 11Register 75 (0x4B): Port 4 Control 11Register 91 (0x5B): Port 5 Control 11Address7

Name

Receive differentialpriority rate control

Description

1, If bit 6 is also ‘1’ this will enable receive rate controlfor this port on low priority packets at the low priorityrate. If bit 5 is also ‘1’, this will enable receive ratecontrol on high priority packets at the high priority rate0, receive rate control will be based on the low priorityrate for all packets on this port.

1, enable port’s low priority receive rate control feature.0, disable port’s low priority receive rate control.1, If bit 7 is also ‘1’ this will enable the port’s high

priority receive rate control feature. If bit 7 is a ‘0’ andbit 6 is a ‘1’, all receive packets on this port will be ratecontrolled at the low priority rate.

0, disable port’s high priority receive rate control feature.1, flow control may be asserted if the port’s low priorityreceive rate is exceeded.

0, flow control is not asserted if the port’s low priorityreceive rate is exceeded.

ModeR/W

Default0

Low priority receiverate control enableHigh priority receiverate control enable

R/WR/W

Low priority receive rateflow control enable

R/W0

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Name

High priority receive

rate flow control enable

Description

1, flow control may be asserted if the port’s high

priority receive rate is exceeded. (To use this, differentialreceive rate control must be on.)

0, flow control is not asserted if the port’s highpriority receive rate is exceeded.

1, will do transmit rate control on both high and lowpriority packets based on the rate counters defined bythe high and low priority packets respectively.0, will do transmit rate control on any packets.

The rate counters defined in low priority will be used.1, enable the port’s low priority transmit rate controlfeature.

0, disable the port’s low priority transmit rate controlfeature.

1, enable the port’s high priority transmit rate controlfeature.

0, disable the port’s high priority transmit rate controlfeature.

ModeR/W

Default0

Micrel2

Transmit differentialpriority rate control

R/W0

Low priority transmitrate control enable

R/W0

High priority transmitrate control enable

R/W0

Register 28 (0x1C): Port 1 Control 12Register 44 (0x2C): Port 2 Control 12Register 60 (0x3C): Port 3 Control 12Register 76 (0x4C): Port 4 Control 12Register 92 (0x5C): Port 5 Control 12

Note:

Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition.

Address7

Name

Disable auto-negotiation

Description

1, disable auto-negotiation, speed and duplex aredecided by bit 6 and 5 of the same register.0, auto-negotiation is on.

1, forced 100BT if AN is disabled (bit 7).0, forced 10BT if AN is disabled (bit 7).

1, forced full-duplex if (1) AN is disabled or (2) AN isenabled but failed.

0, forced half-duplex if (1) AN is disabled or (2) AN isenabled but failed.

ModeR/W

Default0

Forced speedForced duplex

R/WR/W

For port 4 only,there is a specialconfigure pin to setthe default,

Pin PCRS strapoption.

Pull-down(0):Force half-duplex.Pull-up(1):

Force full-duplex.Note:PCRS hasinternal pull down.1

Advertised flowcontrol capabilityAdvertised 100BTfull-duplex capabilityAdvertised 100BThalf-duplex capabilityAdvertised 10BTfull-duplex capability

1, advertise flow control capability.

0, suppress flow control capability from transmissionto link partner.

1, advertise 100BT full-duplex capability.

0, suppress 100BT full-duplex capability fromtransmission to link partner.

1, advertise 100BT half-duplex capability.0, suppress 100BT half-duplex capability fromtransmission to link partner.

1, advertise 10BT full-duplex capability.

0, suppress 10BT full-duplex capability fromtransmission to link partner.

R/W

3R/W1

2R/W1

1R/W0

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Name

Advertised 10BT

half-duplex capability

Description

1, advertise 10BT half-duplex capability.

0, suppress 10BT half-duplex capability fromtransmission to link partner.

ModeR/W

Default1

MicrelRegister 29 (0x1D): Port 1 Control 13Register 45 (0x2D): Port 2 Control 13Register 61 (0x3D): Port 3 Control 13Register 77 (0x4D): Port 4 Control 13Register 93 (0x5D): Port 5 Control 13Address7

NameLED off

Description

1, Turn off all port’s LEDs (LEDx_2, LEDx_1, LEDx_0,where “x” is the port number). These pins will be drivenhigh if this bit is set to one.0, normal operation.1, disable port’s transmitter.0, normal operation.1, restart auto-negotiation.0, normal operation.

1, disable far end fault detection and pattern transmission.0, enable far end fault detection and pattern transmission.1, power down

0, normal operation

1, disable auto MDI/MDIX function.0, enable auto MDI/MDIX function.

1, If auto MDI/MDIX is disabled, force PHY intoMDI mode.

0, Do not force PHY into MDI mode.1, Perform “local loopback,”

(ie. loopback PHYs TX back to RX).0, normal operation.

ModeR/W

Default0

654321

TxidsRestart AN

Disable Far end faultPower down

Disable auto MDI/MDIXForced MDI

R/W0

R/WR/WR/WR/W

0000

R/W0

0Loopback

R/W0

Register 30 (0x1E): Port 1 Status 0Register 46 (0x2E): Port 2 Status 0Register 62 (0x3E): Port 3 Status 0Register 78 (0x4E): Port 4 Status 0Register 94 (0x5E): Port 5 Status 0Address76543210

NameMDIX statusAN doneLink goodPartner flow

control capabilityPartner 100BT

full-duplex capabilityPartner 100BT

half-duplex capabilityPartner 10BT

full-duplex capabilityPartner 10BT

half-duplex capability

Description1, MDI0, MDIX1, AN done0, AN not done1, link good0, link not good

1, link partner flow control capable0, link partner not flow control capable1, link partner 100BT full-duplex capable0, link partner not 100BT full-duplex capable1, link partner 100BT half-duplex capable0, link partner not 100BT half-duplex capable1, link partner 10BT full-duplex capable0, link partner not 10BT full-duplex capable1, link partner 10BT half-duplex capable0, link partner not 10BT half-duplex capable

ModeRORORORORORORORO

Default00000000

December 200349M9999-120403

元器件交易网www.cecb2b.comKS95MRegister 31 (0x1F): Port 1 Status 1

Register 47 (0x2F): Port 2 Status 1Register 63 (0x3F): Port 3 Status 1Register 79 (0x4F): Port 4 Status 1Register 95 (0x5F): Port 5 Status 1Address7-1

NameReserved

Description

1, perform PHY loopback, i.e. loopback MAC’s TXback to RX.

0, normal operation.

1, Far end fault status detected.0, no far end fault status detected.

ModeR/O

Default0

Micrel0Far end faultRO0

Advanced Control Registers

The IPv4 TOS priority control registers implement a fully decoded bit DSCP (Differentiated Services Code Point) registerused to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decodedinto possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If theregister bit is a 1, the priority is high; if it is a 0, the priority is low.

Address7-0

NameDSCP[63:56]

Description

ModeR/W

Default00000000

DSCP[55:48]

R/W

00000000

DSCP[47:40]

R/W

00000000

DSCP[39:32]

R/W

00000000

DSCP[31:24]

R/W

00000000

DSCP[23:16]

R/W

00000000

DSCP[15:8]

R/W

00000000

DSCP[7:0]

R/W

00000000

Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.

MACA[47:40]

R/W

0x00

MACA[39:32]

R/W

0x10

MACA[31:24]

R/W

0xA1

MACA[23:16]

R/W

0xff

MACA[15:8]

R/W

0xff

MACA[7:0]

R/W

0xff

Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters.

M9999-12040350December 2003

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Name

Description

Mode

Default

Reserved

Read High Write LowTable select

Reserved1, read cycle

0, write cycle

00 = static mac address table selected01 = VLAN table selected

10 = dynamic address table selected11 = MIB counter selectedBit 9-8 of indirect address

R/WR/WR/W

00000

Micrel1-0Indirect address highR/W00

Indirect address low

Bit 7-0 of indirect address

R/W

00000000

Note:

write to register 111 will actually trigger a command. Read or write access will be decided by bit 4 of reg110.

Indirect data

Bit 68- of indirect data

R/W

00000

Indirect data

Bit 63-56 of indirect data

R/W

00000000

Indirect data

Bit 55-48 of indirect data

R/W

00000000

Indirect data

Bit 47-40 of indirect data

R/W

00000000

Indirect data

Bit 39-32 of indirect data

R/W

00000000

Indirect data

Bit of 31-24 of indirect data

R/W

00000000

Indirect data

Bit 23-16 of indirect data

R/W

00000000

Indirect data

Bit 15-8 of indirect data

R/W

00000000

Indirect data

Bit 7-0 of indirect data

R/W

00000000

Do not write or read to/from registers 121 to 127. Doing so may prevent proper operation.Micrel internal testing only.

Factory testing

Reserved

Qm_split status

0x0

Factory testing

ReservedDbg[7:0]

0x0

Factory testing

ReservedDbg[12:8]

R/W

0x0

Factory testing

Reserved

R/W

0x0

Factory testing

Reserved

R/W

0x0

M9999-120403

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元器件交易网www.cecb2b.comKS95MAddress

Name

Description

Mode

Default

Factory testing

Reserved

R/W

0x0

MicrelRegister 127 (0x7F): Analog Testing Status7-0

Factory testing

Reserved

0x0

M9999-12040352December 2003

元器件交易网www.cecb2b.comKS95MStatic MAC Address

MicrelKS95M has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make

a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration andlearning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result. If there are DAmatches in both tables, the result from the static table will be used. The static table can only be accessed and controlled byan external SPI master (usually a processor). The entries in the static table will not be aged out by KS95M. An external devicedoes all addition, modification and deletion.

Note:

Register bit assignments are different for static MAC table reads and static MAC table write as shown in the two tables below.

AddressNameDescriptionModeDefault

Format of Static MAC Table for Reads (8 entries)60-57565554

FIDUse FIDReservedOverride

Filter VLAN ID, representing one of the 16 active VLANs1, use (FID+MAC) to look-up in static table.0, use MAC only to look-up in static table.Reserved

1, override spanning tree “transmit enable = 0” or“receive enable = 0” setting. This bit is used forspanning tree implementation.0, no override.

1, this entry is valid, the look-up result will be used0, this entry is not valid.

The 5 bits control the forward ports, example:00001, forward to port 100010, forward to port 2.....

10000, forward to port 5

00110, forward to port 2 and port 3

11111, broadcasting (excluding the ingress port)48 bit mac address

RORORORO

00000N/A0

5352-48

Valid

Forwarding ports

RORO

000000

47-0MAC addressRO0x0

Format of Static MAC Table for Writes (8 entries)59-565554

FIDUse FIDoverride

Filter VLAN ID, representing one of the 16 active VLANs.1, use (FID+MAC) to look-up in static table.0, use MAC only to look-up in static table.1, override spanning tree “transmit enable = 0” or“receive enable = 0” setting. This bit is used forspanning tree implementation.0, no override.

1, this entry is valid, the look-up result will be used.0, this entry is not valid.

The 5 bits control the forward ports, example:00001, forward to port 100010, forward to port 2.....

10000, forward to port 5

00110, forward to port 2 and port 3

11111, broadcasting (excluding the ingress port)48 bit MAC address

WWW

000000

5352-48

valid

Forwarding ports

000000

47-0MAC addressW0x0

Table 12.Static MAC Address Table

December 200353M9999-120403

元器件交易网www.cecb2b.comKS95MExamples:

(1)Static Address Table Read (read the 2nd entry)

Write to reg110 with 0x10 (read static table selected)Write to reg111 with 0x1 (trigger the read operation)Then

Read reg113 (60-56)Read reg114 (55-48)Read reg115 (47-40)Read reg116 (39-32)Read reg117 (31-24)Read reg118 (23-16)Read reg119 (15-8)Read reg120 (7-0)

(2)Static Address Table Write (write the 8th entry)

Write reg113 (59-56)Write reg114 (55-48)Write reg115 (47-40)Write reg116 (39-32)Write reg117 (31-24)Write reg118 (23-16)Write reg119 (15-8)Write reg120 (7-0)

Write to reg110 with 0x00 (write static table selected)Write to reg111 with 0x7 (trigger the write operation)

MicrelM9999-12040354December 2003

元器件交易网www.cecb2b.comKS95MVLAN Address

MicrelVLAN table is used to do VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 =1), this table will be used

to retrieve VLAN information that the ingress packet is associated with. The information includes FID (fiter ID), VID(VLAN ID),VLAN membership described below:

Address

Name

Description

Mode

Default

Format of Static VLAN Table (16 entries)2120-16

ValidMembership

1, the entry is valid0, entry is invalid

Specify which ports are members of the VLAN.If a DA look-up fails (no match in both static and

dynamic tables), the packet associated with this VLANwill be forwarded to ports specified in this field.Eg. 11001 means port 5,4, and 1 are in this VLAN.Filter ID. KS95M supports 16 active VLANs

represented by these four bit fields. FID is the mappedID. If 802.1q VLAN is enabled, the look-up will be basedon FID+DA and FID+SA.EEE 802.1q 12 bit VLAN ID

R/WR/W

111111

15-12FIDR/W0

11-0VIDR/W1

Table 13.VLAN Table

If 802.1q VLAN mode is enabled, KS95M will assign a VID to every ingress packet. If the packet is untagged or tagged witha null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, theVID in the tag will be used. The look-up process will start from the VLAN table look-up. If the VID is not valid, the packet willbe dropped and no address learning will take place. If the VID is valid, the FID is retrieved. The FID+DA and FID+SA lookupsare performed. The FID+DA look-up determines the forwarding ports. If FID+DA fails, the packet will be broadcasted to all themembers (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned.Examples:

(1)VLAN Table Read (read the 3rd entry)

Write to reg110 with 0x14 (read VLAN table selected)Write to reg111 with 0x2 (trigger the read operation)Then

Read reg118 (VLAN table bits 21-16)Read reg119 (VLAN table bits 15-8)Read reg120 (VLAN table bits 7-0)

(2)VLAN Table Write (write the 7th entry)

Write to reg118 (VLAN table bits 21-16)Write to reg119 (VLAN table bits 15-8)Write to reg120 (VLAN table bits 7-0)

Write to reg110 with 0x04 (write static table selected)Write to reg111 with 0x6 (trigger the write operation)

December 200355M9999-120403

元器件交易网www.cecb2b.comKS95MDynamic MAC Address

This table is ready only. The contents are maintained by KS95M only.

Address

Name

Description

Mode

Default

MicrelFormat of Dynamic MAC Address Table (1K entries)6867-58

MAC emptyNo of valid entries

1, there is no valid entry in the table.

0, there are valid entries in the table.Indicates how many valid entries in the table:0x3ff means 1K entries0x1 means 2 entries

0x0 and bit 68 = 0: means 1 entry0x0 and bit 68 = 1: means 0 entry2-bit counters for internal aging.

1, The entry is not ready, retry until this bit is set to 0.0, The entry is ready.

The source port where FID+MAC is learned.000 port 1001 port 2010 port 3011 port 4100 port 5Filter ID

48 bit MAC address

RORO

57-565554-52

Time stampData readySource port

RORORO

0x0

51-4847-0

FID

MAC address

RORO

0x00x0

Table 14.Dynamic MAC Address Table

Examples:

(1)Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size

Write to reg110 with 0x18 (read dynamic table selected)Write to reg111 with 0x0 (trigger the read operation )Then

Read reg112 (68-)

Read reg113 (63-56) ; // the above two registers show # of entriesRead reg114 (55-48) // if bit 55 is 1, restart(reread) from this registerRead reg115 (47-40)Read reg116 (39-32)Read reg117 (31-24)Read reg118 (23-16)Read reg119 (15-8)Read reg120 (7-0)

(2)Dynamic MAC Address Table Read (read the 257th entry), without retrieving # of entries info

Write to reg110 with 0x19 (read dynamic table selected)Write to reg111 with 0x1 (trigger the read operation)Then

Read reg114 (55-48) // if bit 55 is 1, restart (reread) from this registerRead reg115 (47-40)Read reg116 (39-32)Read reg117 (31-24)Read reg118 (23-16)Read reg119 (15-8)Read reg120 (7-0)

M9999-12040356December 2003

元器件交易网www.cecb2b.comKS95MMIB Counters

The MIB counters are provided on per port basis. The indirect memory is as below.

For port 1

Offset0x00x10x20x30x40x50x60x70x80x90xA0xB0xC0xD0xE0xF0x100x110x120x130x140x150x160x170x180x190x1A0x1B0x1C0x1D0x1E0x1F

Counter NameRxLoPriorityByteRxHiPriorityByteRxUndersizePktRxFragmentsRxOversizeRxJabbersRxSymbolErrorRxCRCerrorRxAlignmentErrorRxControl8808PktsRxPausePktsRxBroadcastRxMulticastRxUnicastRxOctetsRx65to127OctetsRx128to255OctetsRx256to511OctetsRx512to1023OctetsRx1024to1522OctetsTxLoPriorityByteTxHiPriorityByteTxLateCollisionTxPausePktsTxBroadcastPktsTxMulticastPktsTxUnicastPktsTxDeferredTxTotalCollisionTxExcessiveCollisionTxSingleCollisionTxMultipleCollision

Description

Rx lo-priority (default) octet count including bad packets.Rx hi-priority octet count including bad packets.Rx undersize packets w/ good CRC.

Rx fragment packets w/ bad CRC, symbol errors or alignment errors.Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes).

Rx packets longer than 1522B w/ either CRC errors, alignment errors, or symbol errors.(Depends on max packet size setting)

Rx packets w/ invalid data symbol and legal packet size.

Rx packets within (,1522) bytes w/ an integral number of bytes and a bad CRC.(Upper limit depends on max packet size setting)

Rx packets within (,1522) bytes w/ a non-integral number of bytes and a bad CRC.(Upper limit depends on max packet size setting)

The number of MAC control frames received by a port with 88-08h in EtherType field.The number of PAUSE frames received by a port. PAUSE frame is qualified with

EtherType (88-08h), DA, control opcode (00-01), data length (B min), and a valid CRC.Rx good broadcast packets (not including errored broadcast packets or valid multicastpackets).

Rx good multicast packets (not including MAC control frames, errored multicast packets orvalid broadcast packets).Rx good unicast packets.

Total Rx packets (bad packets included) that were octets in length.

Total Rx packets (bad packets included) that are between 65 and 127 octets in length.Total Rx packets (bad packets included) that are between 128 and 255 octets in length.Total Rx packets (bad packets included) that are between 256 and 511 octets in length.Total Rx packets (bad packets included) that are between 512 and 1023 octets in length.Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length.(Upper limit depends on max packet size setting)Tx lo-priority good octet count, including PAUSE packets.Tx hi-priority good octet count, including PAUSE packets.

The number of times a collision is detected later than 512 bit-times into the Tx of a packet.The number of PAUSE frames transmitted by a port.

Tx good broadcast packets (not including errored broadcast or valid multicast packets).

MicrelTx good multicast packets (not including errored multicast packets or valid broadcast packets).Tx good unicast packets.

Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium.Tx total collision, half-duplex only.

A count of frames for which Tx fails due to excessive collisions.

Successfully Tx frames on a port for which Tx is inhibited by exactly one collision.Successfully Tx frames on a port for which Tx is inhibited by more than one collision.

Table 15.Port-1 MIB Counter Indirect Memory Offsets

December 200357M9999-120403

元器件交易网www.cecb2b.comKS95MFor port 2, the base is 0x20, same offset definition (0x20-0x3f)

For port 3, the base is 0x40, same offset definition (0x40-0x5f)For port 4, the base is 0x60, same offset definition (0x60-0x7f)For port 5, the base is 0x80, same offset definition (ox80-0x9f)

Address

Name

Description

Mode

Default

MicrelFormat of Per Port MIB Counters (16 entries)313029-0

OverflowCount ValidCounter values

1, Counter overflow0, No Counter overflow1, Counter value is valid0, Counter value is not validCounter value

RORORO

000

Offset0x1000x1010x1020x1030x1040x1050x1060x1070x1080x109

Counter NamePort1 Tx Drop PacketsPort2 Tx Drop PacketsPort3 Tx Drop PacketsPort4 Tx Drop PacketsPort5 Tx Drop PacketsPort1 Rx Drop PacketsPort2 Rx Drop PacketsPort3 Rx Drop PacketsPort4 Rx Drop PacketsPort5 Rx Drop Packets

Description

Tx packets dropped due to lack of resourcesTx packets dropped due to lack of resourcesTx packets dropped due to lack of resourcesTx packets dropped due to lack of resourcesTx packets dropped due to lack of resourcesRx packets dropped due to lack of resourcesRx packets dropped due to lack of resourcesRx packets dropped due to lack of resourcesRx packets dropped due to lack of resourcesRx packets dropped due to lack of resources

Table 16.All Port Dropped Packet MIB Counters

Address

Name

Description

Mode

Default

Format of All Port Dropped Packet MIB Counters30-1615-0

ReservedCounter values

ReservedCounter value

N/ARO

N/A0

Note:

All port dropped packet MIB counters do not indicate overflow or validity; therefore the application must keep track of overflow and valid conditions.

Examples:

(1)MIB counter read (read port 1 rx counter)

Write to reg110 with 0x1c (read MIB countersselected)

Write to reg111 with 0xe (trigger the read operation)Then

Read reg117 (counter value 31-24)

// If bit 31 = 1, there was a counter overflow.// If bit 30 = 0, restart (reread) from this register.Read reg118 (counter value 23-16)Read reg119 (counter value 15-8)Read reg120 (counter value 7-0)

M9999-12040358December 2003

元器件交易网www.cecb2b.comKS95M(2)MIB counter read (read port 2 rx counter)

Write to reg110 with 0x1c(read MIB counter selected)Write to reg111 with 0x2e(trigger the read operation )Then

Read reg117 (counter value 31-24)

// If bit 31 = 1, there was a counter overflow.// If bit 30 = 0, restart (reread) from this register.Read reg118 (counter value 23-16)Read reg119 (counter value 15-8)Read reg120 (counter value 7-0)

(3)MIB counter read (read port 1 tx drop packets)

Write to reg 110 with 0x1dWrite to reg 111 with 0x00Then

Read reg119 (counter value 15-8)Read reg120 (counter value 7-0)

MicrelNote:

To read out all the counters, the best performance over the SPI bus is (160+3)×8×200 = 260ms, where there are 160 register, 3 overhead, 8 clocksper access, at 5MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters atleast every 30 seconds. The per port MIB counters are designed as “read clear.” A per port MIB counter will be cleared after it is accessed. All portdropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on thesecounters.

December 200359M9999-120403

元器件交易网www.cecb2b.comKS95MMIIM Registers

Micrel(All the registers defined in this section can be also accessed via the SPI interface. Note:different mapping mechanisms used

for MIIM and SPI). The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port4, “0x5” for port 5. The “REGAD” supported are 0,1,2,3,4,5.

Address

Name

Description

Mode

Default

Soft resetLoop backForce 100AN enablePower downPHY IsolateRestart ANForce full-duplexCollision testReservedReservedForce MDI

Disable Auto MDI/MDIXDisable far end faultDisable transmitDisable LED

1, Force MDI

0, Normal operation1, Disable auto MDI/MDIX0, Normal operation

1, Disable far end fault detection0, Normal operation1, Disable transmit0, Normal operation1, Disable LED

0, Normal operationNot supported

1, Loop back mode (loop back at MAC)0, Normal operation1, 100Mbps0, 10Mbps

1, Auto-negotiation enabled0, Auto-negotiation disabled1, Power down

0, Normal operationNot supported

1, Restart auto-negotiation0, Normal operation1, Full duplex0, Half-duplexNOT SUPPORTED

ROR/WR/WR/WR/WROR/WR/WROROROR/WR/WR/WR/WR/W

0011000000000000

M9999-12040360December 2003

元器件交易网www.cecb2b.comKS95MAddress

Name

Description

Mode

Default

T4 capable100 Full capable100 Half capable10 Full capable10 Half capableReserved

Preamble suppressedAN completeFar end faultAN capableLink statusJabber testExtended capable

NOT SUPPORTED

1, Auto-negotiation complete

0, Auto-negotiation not completed1, Far end fault detected0, No far end fault detected1, Auto-negotiation capable0, Not Auto-negotiation capable1, Link is up0, Link is downNOT SUPPORTED

0, Not extended register capable0, Not 100 BaseT4 capable

1, 100BaseTX full-duplex capable

0, Not capable of 100BaseTX full-duplex1, 100BaseTX half-duplex capable0, Not 100BaseTX half-duplex capable1, 10BaseT full-duplex capable0, Not 10BaseT full-duplex capable1, 10BaseT half-duplex capable0, 10BaseT half-duplex capable

RORORORORORORORORORORORORO

0111100001000

MicrelRegister 2: PHYID HIGH15-0

Phyid high

High order PHYID bits

0x0022

Phyid low

Low order PHYID bits

0x1450

Next pageReservedRemote faultReservedPauseReservedAdv 100 FullAdv 100 HalfAdv 10 FullAdv 10 HalfSelector field

1, Advertise 100 full-duplex ability

0, Do not advertise 100 full-duplex ability1, Advertise 100 half-duplex ability

0, Do not advertise 100 half-duplex ability1, Advertise 10 full-duplex ability

0, Do not advertise 10 full-duplex ability1, Advertise 10 half-duplex ability

0, Do not advertise 10 half-duplex ability802.3

1, Advertise pause ability

0, Do not advertise pause abilityNOT SUPPORTEDNOT SUPPORTED

ROROROROR/WR/WR/WR/WR/WR/WRO

000010111100001

December 200361M9999-120403

元器件交易网www.cecb2b.comKS95MAddress

Name

Description

Mode

Default

Next pageLP ACKRemote faultReservedPauseReservedAdv 100 FullAdv 100 HalfAdv 10 FullAdv 10 HalfReserved

Link partner 100 full capabilityLink partner 100 half capabilityLink partner 10 full capabilityLink partner 10 half capabilityLink partner pause capabilityNOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED

RORORORORORORORORORORO

000000000000001

MicrelM9999-12040362December 2003

元器件交易网www.cecb2b.comKS95MAbsolute Maximum Ratings(1)

Supply Voltage

(VDDAR, VDDAP, VDDC, VDDAT).................–0.5V to +2.4V(VDDIO)....................................................–0.5V to +4.0VInput Voltage...............................................–0.5V to +4.0VOutput Voltage............................................–0.5V to +4.0VLead Temperature (soldering, 10 sec.).....................270°CStorage Temperature (TS).......................–55°C to +150°C

MicrelOperating Ratings(2)

Supply Voltage

(VDDAR, VDDAP, VDDC).............................+1.7V to +1.9V(VDDAT)....................................................+2.4V to +2.6V(VDDIO).........................................................+3.0 to +3.6Ambient Temperature (TA)

Commercial..............................................–0°C to +70°CIndustrial.................................................–40°C to +85°CPackage Thermal Resistance(3)

PQFP (θJA) No Air Flow.................................59.47°C/W

Electrical Characteristics(4)

VIN = 1.8V/2.5V; TA = 0°C to +70°C; unless noted, bold values indicate –40°C ≤ TA ≤ +85°C; unless noted.Symbol

Parameter

Condition

Min

Typ

Max

Units

100BaseTx Operation—All Ports 100% UtilizationIDXIDDCIDDIOIDXIDDCIDDIOIDXIDDCIDDIOTTL InputsVIHVILIIN

TTL OutputsVOHVOL|IOZ|VOVIMBtr, tt

Output High VoltageOutput Low VoltageOutput Tri-State Leakage

IOH = –8mAIOL = 8mA

VIN = GND ~ VDDIO

100Ω termination on the differential output100Ω termination on the differential output

300.95VDDIO–0.4

+0.410

VVµA

Input High VoltageInput Low Voltage

Input Current

(Excluding Pull-up/Pull-down)

VIN = GND ~ VDDIO

–101/2 (VDDIO)+0.4V

1/2 (VDDIO)–0.4V

VVµA

100BaseTX (Transmitter)

VDDATVDDIOVDDATVDDC, VDDAPVDDIOVDDATVDDC, VDDAPVDDIO

22915717

25023030

mAmAmA

100BaseTX (Digital Core/PLL+Analog Rx)VDDC, VDDAP, VDDAR100BaseTX (Digital IO)

10BaseTx Operation—All Ports 100% Utilization

10BaseTX (Transmitter)

10BaseTX (Digital Core+Analog Rx)10BaseTX (Digital IO)

3501026

37518015

mAmAmA

Auto-Negotiation Mode

10BaseTX (Transmitter)

10BaseTX (Digital Core+Analog Rx)10BaseTX (Digital IO)

2510817

4018020

mAmAmA

100BaseTX Transmit (measured differentially after 1:1 transformer)

Peak Differential Output VoltageOutput Voltage ImbalanceRise/Fall Time

Rise/Fall Time Imbalance

Notes:

1.Exceeding the absolute maximum rating may damage the device.

2.The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Groundto VDD).3.No HS (heat spreader) in package.4.Specification for packaged product only.

1.05250.5

V%nsns

December 200363M9999-120403

元器件交易网www.cecb2b.comKS95MSymbol

Parameter

Condition

Min

Typ

Max

100BaseTX Transmit (measured differentially after 1:1 transformer)

Duty Cycle DistortionOvershoot

VSET

Reference Voltage of ISETOutput Jitters

10BaseTX ReceiveVSQVP

Squelch Threshold

5MHz square wave

400

Peak-to-peak

0.50.7

1.4±0.55

MicrelUnits

ns%Vns

10BaseT Transmit (measured differentially after 1:1 transformer) VDDAT = 2.5V

Peak Differential Output VoltageJitters AddedRise/Fall Times

100Ω termination on the differential output100Ω termination on the differential output

282.3

±3.530

VVns

M9999-120403December 2003

元器件交易网www.cecb2b.comKS95MTiming Diagrams

ts1Receive Timingtcyc1th1MicrelSCLSDAFigure 12. EEPROM Interface Input Receive Timing Diagram

tcyc1Transmit TimingSCLSDAtov1Figure 13. EEPROM Interface Output Transmit Timing Diagram

SymboltCYC1tS1tH1tOV1

ParameterClock CycleSet-Up TimeHold TimeOutput Valid

MinTyp16384

MaxUnitsnsnsns

20204096

4112

4128

Table 17.EEPROM Timing Parameters

December 200365M9999-120403

元器件交易网www.cecb2b.comKS95Mts2Receive Timingtcyc2th2MicrelMTXCMTXENMTXD[0]Figure 14.SNI Input Timing

tcyc2Transmit TimingMRXCMRXDVMCOLMRXD[0]tov2Figure 15.SNI Output Timing

SymboltCYC2tS2tH2tO2

ParameterClock CycleSet-Up TimeHold TimeOutput Valid

MinTyp100

MaxUnitsnsnsns

1000

Table 18.SNI Timing Parameters

M9999-12040366December 2003

元器件交易网www.cecb2b.comKS95Mts3Receive Timingtcyc3th3MicrelMRXCLKMTXENMTXERMTXD[3:0]Figure 16.MAC Mode MII Timing–Data Received from MII

tcyc3Transmit TimingMTXCLKMRXDVMRXD[3:0]tov3Figure 17.MAC Mode MII Timing–Data Transmitted from MII

SymboltCYC3tCYC3tS3tH3tOV3

ParameterClock CycleClock CycleSet-Up TimeHold TimeOutput Valid

(100BaseT)(10BaseT)

MinTyp40400

MaxUnitsnsnsnsns

1057

Table 19.MAC Mode MII Timing Parameters

December 200367M9999-120403

元器件交易网www.cecb2b.comKS95Mts4Receive Timingtcyc4th4MicrelMTXCLKMTXENMTXERMTXD[3:0]Figure 18.PHY Mode MII Timing–Data Received from MII

tcyc4Transmit TimingMRXCLKMRXDVMRXD[3:0]tov4Figure 19.PHY Mode MII Timing–Data Transmitted from MII

SymboltCYC4tCYC4tS4tH4tOV4

ParameterClock CycleClock CycleSet-Up TimeHold TimeOutput Valid

(100BaseT)(10BaseT)

MinTyp40400

MaxUnitsnsnsnsns

10018

Table 20.PHY Mode MII Timing Parameters

M9999-12040368December 2003

元器件交易网www.cecb2b.comKS95MtSHSLMicrelSPIS_NtCHSLSPICtDVCHtCHDXSPIDMSBtDLDHtDHDLSPIQHigh ImpedancetCLCHLSBtSLCHtCHSHtSHCHtCHCLFigure 20.SPI Input Timing

SymbolfCtCHSLtSLCHtCHSHtSHCHtSHSLtDVCHtCHDXtCLCHtCHCLtDLDHtDHDL

ParameterClock Frequency

SPIS_N Inactive Hold TimeSPIS_N Active Set-Up TimeSPIS_N Active Hold TimeSPIS_N Inactive Set-Up TimeSPIS_N Deselect TimeData Input Set-Up TimeData Input Hold TimeClock Rise TimeClock Fall TimeData Input Rise TimeData Input Fall Time

MinTypMax5

UnitsMHznsnsnsnsnsnsns

909090901002030

1111

µsµsµsµs

Table 21.SPI Input Timing Parameters

December 200369M9999-120403

元器件交易网www.cecb2b.comKS95MMicrelSPIS_NtCHSPICtCLQVtCLQXSPIQtQLQHtQHQLSPIDLSBtCLtSHQZFigure 21.SPI Output Timing

SymbolfCtCLQXtCLQVtCHtCLtQLQHtQHQLtSHQZ

ParameterClock FrequencySPIQ Hold TimeClock Low to SPIQ ValidClock High TimeClock Low TimeSPIQ Rise TimeSPIQ Fall TimeSPIQ Disable Time

MinTypMax5

UnitsMHznsnsnsns

0060

9090

5050100

nsnsns

Table 22.SPI Output Timing Parameters

M9999-12040370December 2003

元器件交易网www.cecb2b.comKS95MSupply

Voltage

tsrMicrelRST_N

tcstchStrap-InValue

trcStrap-In /Output Pin

Figure 22.Reset Timing

SymboltSRtCStCHtRC

Parameter

Stable Supply Voltages to Reset HighConfiguration Set-Up TimeConfiguration Hold TimeReset to Strap-In Pin Output

Min10505050

TypMaxUnitsmsnsnsns

Table 23.Reset Timing Parameters

December 200371M9999-120403

元器件交易网www.cecb2b.comKS95MSelection of Isolation Transformer(1)

MicrelOne simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-modechoke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.

Characteristics NameTurns Ratio

Open-Circuit Inductance (min.)Leakage Inductance (max.)Inter-Winding Capacitance (max.)D.C. Resistance (max.)Insertion Loss (max.)HIPOT (min.)

Note:

1.The IEEE 802.3u standard for 100BaseTX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB canbe compensated by increasing the line drive current by means of reducing the ISET resistor value.

Value1 CT : 1 CT350µH0.4µH12pF0.9Ω1.0dB1500Vrms

Test Condition

100mV, 100 KHz, 8mA1MHz (min.)

0MHz to 65MHz

The following transformer vendors provide compatible magnetic parts for Micrel’s device:

4-Port IntegratedVendorPartPulseBel FuseYCLTranspowerDeltaLanKom

H11558-5999-Q9PH4066HB826-2LF8731SQ-H48W

Auto

MDIXYesYesYesYesYesYes

Numberof Ports

444444

Single Port

VendorPulseBel FuseYCLTranspowerDeltaLanKom

PartH1102S558-5999-U7PT163020HB726LF8505LF-H41S

AutoMDIXYesYesYesYesYesYes

Numberof Ports

111111

Table 24.Qualified Magnetics Lists

M9999-12040372December 2003

元器件交易网www.cecb2b.comKS95MPackage Information

Micrel128-Pin PQFP (PQ)

MICREL, INC.1849 FORTUNE DRIVESAN JOSE, CA95131

USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product canreasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant intothe body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’suse or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

December 200373M9999-120403

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